Method for Generating Descriptive Trace Gaps

1. A debug trace gathering system comprising: a First In, First Out (FIFO) buffer memory having an input receiving trace data, an output of buffered data and a full output generating a FIFO full signal when said FIFO buffer memory is full; a counter connected to said FIFO buffer memory, said counter counting incoming data while said FIFO full signal indicates said FIFO buffer memory is full; and a trace encoder and scheduler connected to said FIFO buffer memory and said counter, said trace encoder and scheduler operable to output trace data corresponding to said buffered data while said FIFO full signal indicates said FIFO buffer memory is not full, not output trace data corresponding to said buffered data while said FIFO full signal indicates said FIFO buffer memory is full, and outputting a data gap marker upon said FIFO full signal indicating and said FIFO buffer is not full following an indication that said FIFO buffer is full, said data gap marker including an accumulated count of said counter while said FIFO full signal indicated said FIFO buffer memory was full indicating an amount of data lost.

2. The debug trace gathering system of claim 1 , further comprising: at least one further trace data stream; for each of said at least one further trace data stream a further FIFO buffer memory, a further counter and a further a trace encoder and scheduler.

3. A debug trace gathering system comprising: a First In, First Out (FIFO) buffer memory having an input receiving trace data, an output of buffered data and a full output generating a FIFO fullness signal indicating a current FIFO fullness state; a dead window throttle connected to said FIFO buffer memory, said dead window throttle operable to open a dead window for a predetermined period to time when FIFO fullness signals indicated a preprogrammed threshold of fullness; a trace encoder and scheduler connected to said FIFO buffer memory and said dead window throttle, said trace encoder and scheduler operable to output trace data corresponding to said buffered data while a dead window is not open, not output trace data corresponding to said buffered data while said dead window is open, and outputting a data gap marker upon said dead window opening.

4. The debug trace gathering system of claim 3 , wherein: said predetermined period of time said dead windows is open is user programmable.

5. The debug trace gathering system of claim 3 , further comprising: a gap detect unit connected to said FIFO buffer, memory, said dead window throttle and said trace encoder and scheduler, said gap detect unit operable to determine an amount of trace data received during while a dead window is open; and wherein said gap marker of said trace encoder and scheduler indicates said amount of trace data received during while a dead window is open.

6. A debug trace gathering system comprising: a First In, First Out (FIFO) buffer memory having an input receiving trace data, an output of buffered data and a full output generating a FIFO fullness signal indicating a current FIFO fullness state; a real-time throttle unit having an input receiving said trace data, said real-tome throttle unit generating an active throttle signal when trace bus utilization exceeds a programmable threshold; a trace encoder and scheduler connected to said FIFO buffer memory and said dead window throttle, said trace encoder and scheduler operable to output trace data corresponding to said buffered data while said throttle signal is not active, not output trace data corresponding to said buffered data while said throttle signal is active, and outputting a data gap marker upon said throttle signal becoming inactive.

7. The debug trace gathering system of claim 6 , further comprising: a gap detect unit connected to said FIFO buffer, memory, said real-time throttle unit and said trace encoder and scheduler, said gap detect unit operable to determine an amount of trace data received during while a dead window is open; and wherein said gap marker of said trace encoder and scheduler indicates said amount of trace data received during while said throttle signal is active.

8. A debug trace gathering system comprising: a First In, First Out (FIFO) buffer memory having an input receiving trace data, an output of buffered data and a full output generating a FIFO fullness signal indicating a current FIFO fullness state; a real-time throttle unit having an input receiving said trace data, said real-time throttle unit generating an active throttle signal when trace bus utilization exceeds a programmable threshold; a dead window unit opening a dead window upon an active throttle signal; a trace encoder and scheduler connected to said FIFO buffer memory and said dead window throttle, said trace encoder and scheduler operable to output trace data corresponding to said buffered data while a dead window is not open, not output trace data corresponding to said buffered data while said dead window is open, and outputting a data gap marker upon said dead window opening.

9. The debug trace gathering system of claim 8 , further comprising: a gap detect unit connected to said FIFO buffer, memory, said real-time throttle unit and said trace encoder and scheduler, said gap detect unit operable to determine an amount of trace data received during while a dead window is open; and wherein said gap marker of said trace encoder and scheduler indicates said amount of trace data received during while said throttle signal is active.