Parallel Bit Reversal Devices and Methods

1. A parallel bit reversal device comprising: a memory for storing data; a butterfly computation and control unit coupled to the memory via a data bus; and a parallel bit reversal unit configured to bit-reversing butterfly group data used by the butterfly computation and control unit wherein the parallel bit reversal unit comprises: an address reversing logic coupled to the butterfly computation and control unit and configured to perform mirror reversal and right-shift operations on a read address from the butterfly computation and control unit; an address selector; and a multi-granularity parallel memory coupled to the address selector and the butterfly computation and control unit, and configured to receive an address outputted from the address selector and receive written data and a read/write (R/W) granularity value outputted from the butterfly computation and control unit.

2. The parallel bit reversal device of claim 1 , wherein the parallel bit reversal unit further comprises a data reversal network coupled to the multi-granularity parallel memory to receive read data from the multi-granularity parallel memory.

3. The parallel bit reversal device of claim 2 , wherein the data reversal network is configured to bit-reversing data within a butterfly group.

4. The parallel bit reversal device of claim 2 , wherein the address selector is coupled to both the butterfly computation and control unit and the address reversing logic, and is configured to select a R/W address to be outputted to the memory.

5. A parallel bit reversal method in a parallel bit reversal device comprising a parallel bit reversal unit and a memory, the parallel bit reversal unit comprising a multi-granularity parallel memory, the method comprises: transferring data from the memory to the multi-granularity parallel memory, dividing equally the transferred data in a natural order into 2 n groups, and storing them sequentially in 2 n memory blocks of the multi-granularity parallel memory, n is a positive integer; reversing a data group index of each of the data groups, while keeping an intra-group index of the data group unchanged; shifting the intra-group index to a higher position while keeping the intra-group index and the data group index unchanged; and reversing the intra-group index while keeping the data group index unchanged.

6. The parallel bit reversal method of claim 5 , wherein the parallel bit reversal device further comprises a butterfly computation and control unit under control of which the above steps are performed.

7. The parallel bit reversal method of claim 6 , wherein the parallel bit reversal unit further comprises an address reversing logic and an address selector, and the butterfly computation and control unit is coupled to the address reserving logic via a shift indication line and a read address line.

8. The parallel bit reversal method of claim 7 , wherein at the step of reversing a data group index of each of the data groups, the value on the shift indication line is set as A-n, A being a bit width of the read address line, and the read address on the read address line is set as the data group index; the address selector selects an output from the address reversing logic as a R/W address for the memory.

9. The parallel bit reversal method of claim 8 , wherein at the step of reversing the intra-group index, the data read from the multi-granularity parallel memory is bit reversed in the data reversal network and outputted to the butterfly computation and control unit.

10. The parallel bit reversal method of claim 9 , wherein after the step of reversing the intra-group index, a number 2 n of bit-reversed data are obtained at the output of the data reversal network and directly used for butterfly computation.