Devices and Methods for Facilitating Data Inversion to Limit Both Instantaneous Current and Signal Transitions

1. An electronic device comprising at least one encoder, the encoder comprising: a data bus interface adapted to be coupled with a data bus to facilitate a transmission of data bits; and a processing circuit coupled with the data bus interface, the processing circuit adapted to: perform a first encoding scheme on a group of data bits to be transmitted on a data bus via the data bus interface to generate a first group of encoded data bits, wherein the first encoding scheme is performed based on a number of transitions within the group of data bits; and perform a second encoding scheme on the first group of encoded data bits based on a number of data bits within the first group of encoded data bits exhibiting a predetermined state to generate a second group of encoded data bits.

2. The electronic device of claim 1 , wherein the processing circuit adapted to perform the first encoding scheme on the group of data bits comprises the processing circuit adapted to: determine a number of transitions on each data channel of a plurality of data channels on the data bus over a duration of a predetermined number of data bits; and invert every other data bit of the predetermined number of data bits on a data channel when the number of transitions on the data channel is determined to be above a transition threshold.

3. The electronic device of claim 1 , wherein the processing circuit adapted to perform the second encoding scheme on the first group of encoded data bits comprises the processing circuit adapted to: determine a number of data bits set to a predetermined state on each data channel of a plurality of data channels on the data bus over a duration of a predetermined number of data bits; and invert the data bits of the predetermined number of data bits on a data channel when the number of data bits set to the predetermined state on the data channel is above a state threshold.

4. The electronic device of claim 1 , wherein the processing circuit is further adapted to: set a plurality of first encoding flags to indicate which data bits are encoded by the first encoding scheme; and set a plurality of second encoding flags to indicate which data bits are encoded by the second encoding scheme.

5. The electronic device of claim 4 , wherein the first encoding flags are either set as data bits in an additional data channel, wherein each data bit of the additional data channel is associated with a respective data channel of the group of data bits, or data bits added to each respective data channel.

6. The electronic device of claim 4 , wherein the second encoding flags are either set as data bits in an additional data channel, wherein each data bit of the additional data channel is associated with a respective data channel of the group of data bits, or data bits added to each respective data channel.

7. The electronic device of claim 1 , wherein the processing circuit is adapted to: perform the second encoding scheme on the group of data bits prior to performing the first encoding scheme on the group of data bits.

8. A method operational on an electronic device, comprising: performing a first encoding scheme on a group of data bits to be transmitted over a data bus to generate a first group of encoded data bits, wherein the first encoding scheme is performed based on a number of transitions within the group of data bits; and performing a second encoding scheme on the first group of encoded data bits based on a number of data bits within the first group of encoded data bits exhibiting a predetermined state to generate a second group of encoded data bits.

9. The method of claim 8 , wherein performing the first encoding scheme on the group of data bits comprises: determining a number of transitions on each data channel of a plurality of data channels on the data bus over a duration of a predetermined number of data bits; and inverting every other data bit of the predetermined number of data bits on a data channel when the number of transitions on the data channel is determined to be above a transition threshold.

10. The method of claim 8 , wherein performing the second encoding scheme on the first group of encoded data bits comprises: determining a number of data bits set to a predetermined state on each data channel of a plurality of data channels on the data bus over a duration of a predetermined number of data bits; and inverting the data bits of the predetermined number of data bits on a data channel when the number of data bits set to the predetermined state on the data channel is above a state threshold.

11. The method of claim 8 , further comprising: setting first encoding flags to indicate which data bits are encoded by the first encoding scheme; and setting second encoding flags to indicate which data bits are encoded by the second encoding scheme.

12. The method of claim 11 , wherein setting the first encoding flags comprises: setting data bits in an additional data channel, wherein each data bit of the additional data channel is associated with a respective data channel of the group of data bits, or setting data bits added to each respective data channel.

13. The method of claim 11 , wherein setting the second encoding flags comprises: setting data bits in an additional data channel, wherein each data bit of the additional data channel is associated with a respective data channel of the group of data bits, or setting data bits added to each respective data channel.

14. The method of claim 8 , wherein performing the first encoding scheme on the group of data bits comprises: performing the first encoding scheme on the group of data bits after performing the second encoding scheme on the group of data bits.

15. An electronic device, comprising: means for performing a first encoding scheme on a group of data bits to be transmitted over a data bus to generate a first group of encoded data bits, wherein the first encoding scheme is performed based on a number of transitions within the group of data bits; and means for performing a second encoding scheme on the first group of encoded data bits based on a number of data bits within the first group of encoded data bits exhibiting a predetermined state to generate a second group of encoded data bits.

16. The electronic device of claim 15 , wherein performing the first encoding scheme on the group of data bits comprises: determining a number of transitions on each data channel of a plurality of data channels on the data bus over a duration of a predetermined number of data bits; and inverting every other data bit of the predetermined number of data bits on a data channel when the number of transitions on the data channel is determined to be above a transition threshold.

17. The electronic device of claim 15 , wherein performing the second encoding scheme on the first group of encoded data bits comprises: determining a number of data bits set to a predetermined state on each data channel of a plurality of data channels on the data bus over a duration of a predetermined number of data bits; and inverting the data bits of the predetermined number of data bits on a data channel when the number of data bits set to the predetermined state on the data channel is above a state threshold.

18. The electronic device of claim 15 , further comprising: means for setting a plurality of first encoding flags to indicate which data bits are encoded by the first encoding scheme; and means for setting a plurality of second encoding flags to indicate which data bits are encoded by the second encoding scheme.

19. A processor-readable storage medium, comprising programming for causing a processing circuit to: employ a first encoding scheme on a group of data bits to be transmitted over a data bus to generate a first group of encoded data bits, wherein the first encoding scheme is performed based on a number of transitions within the group of data bits; and employ a second encoding scheme on the first group of encoded data bits based on a number of data bits within the first group of encoded data bits exhibiting a predetermined state to generate a second group of encoded data bits.

20. The processor-readable storage medium of claim 19 , wherein the first encoding scheme comprises: determining a number of transitions on each data channel of a plurality of data channels on the data bus over a duration of a predetermined number of data bits; and inverting every other data bit of the predetermined number of data bits on a data channel when the number of transitions on the data channel is determined to be above a transition threshold.

21. The processor-readable storage medium of claim 19 , wherein the second encoding scheme comprises: determining a number of data bits set to a predetermined state on each data channel of a plurality of data channels on the data bus over a duration of a predetermined number of data bits; and inverting the data bits of the predetermined number of data bits on a data channel when the number of data bits set to the predetermined state on the data channel is above a state threshold.

22. The processor-readable storage medium of claim 19 , further comprising programming for causing a processing circuit to: set a plurality of first encoding flags to indicate which data bits are encoded by the first encoding scheme; and set a plurality of second encoding flags to indicate which data bits are encoded by the second encoding scheme.

23. An electronic device comprising at least one encoder, the encoder comprising: a transition detector adapted to determine a number of transitions on a plurality of data channels of a data bus for a predetermined number of cycles; a state detector adapted to determine a number of cycles set to a predetermined state on each data channel of the plurality of data channels for the predetermined number of cycles; and an invertor adapted to: invert data bits corresponding to every other cycle of the predetermined number of cycles on a data channel when the number of transitions on the data channel is determined to be above a transition threshold; and invert data bits corresponding to the cycles of the predetermined number of cycles on a data channel when the number of cycles in which data bits are set to the predetermined state on the data channel is determined to be above a state threshold.

24. The electronic device of claim 23 , wherein the invertor is further adapted to: set a plurality of transition inversion encoding flags to indicate on each data channel whether every other cycle is inverted in response to the determination that the number of transitions is above the transition threshold; and set a plurality of state inversion encoding flag to indicate on each data channel whether the cycles are inverted in response to the determination that the number of cycles set to the predetermined state is above the state threshold.

25. The electronic device of claim 24 , wherein the invertor is adapted to: set the plurality of transition inversion encoding flags on a first flag channel, wherein each cycle on the first flag channel is associated with a respective data channel; and set the plurality of state inversion encoding flags on a second flag channel, wherein each cycle on the second flag channel is associated with a respective data channel.

26. The electronic device of claim 24 , wherein the invertor is adapted to: set the plurality of transition inversion encoding flags on a first flag channel, wherein two or more consecutive cycles on the first flag channel are associated with a respective data channel; and set the plurality of state inversion encoding flags on a second flag channel, wherein two or more consecutive cycles on the second flag channel are associated with a respective data channel.

27. The electronic device of claim 24 , wherein the invertor is adapted to: set the plurality of transition inversion encoding flags and the plurality of state inversion encoding flags on the same flag channel.

28. The electronic device of claim 24 , wherein the invertor is adapted to: set a respective transition inversion encoding flag on each data channel as an additional cycle; and set a respective state encoding inversion flag on each data channel as another additional cycle.

29. The electronic device of claim 24 , wherein the invertor is adapted to: set the plurality of transition inversion encoding flags on a flag channel, wherein each cycle on the flag channel is associated with a respective data channel; and set a state inversion encoding flag as an additional cycle on each data channel and the flag channel.

30. A method operational on an electronic device, comprising: determining a number of transitions on a plurality of data channels of a data bus for a predetermined number of cycles; inverting data bits corresponding to every other cycle of a data channel when the number of transitions on the data channel is determined to be above a transition threshold; setting a respective transition inversion encoding flag associated with each data channel to indicate whether the data bits corresponding to every other cycle of the associated data channel have been inverted; determining a number of cycles in which data bits are set to a predetermined state on each data channel of the plurality of data channels for the predetermined number of cycles; inverting the data bits in the cycles of a data channel when the number of cycles in which data bits are set to the predetermined state on the data channel is above a state threshold; and setting a respective state inversion encoding flag associated with each data channel to indicate whether the data bits in the cycles of the associated data channel are inverted.

31. The method of claim 30 , wherein setting the respective transition inversion encoding flag associated with each data channel to indicate whether the data bits corresponding to every other cycle of the associated data channel have been inverted comprises: setting each of the transition inversion encoding flags on a flag channel, wherein each cycle on the flag channel is associated with a respective data channel.

32. The method of claim 30 , wherein setting the respective transition inversion encoding flag associated with each data channel to indicate whether the data bits corresponding to every other cycle of the associated data channel have been inverted comprises: setting the respective transition inversion encoding flag on the associated data channel as an additional cycle.

33. The method of claim 30 , wherein setting the respective state inversion encoding flag associated with each data channel to indicate whether the data bits of the associated data channel are inverted comprises: setting each of the state inversion encoding flags on a flag channel, wherein each cycle on the flag channel is associated with a respective data channel.

34. The method of claim 30 , wherein setting the respective state inversion encoding flag associated with each data channel to indicate whether the data bits of the associated data channel are inverted comprises: setting the respective state inversion encoding flag on the associated data channel as an additional cycle.

35. An electronic device, comprising: means for determining a number of transitions on a plurality of data channels of a data bus for a predetermined number of cycles; means for inverting data bits corresponding to every other cycle of a data channel when the number of transitions on the data channel is determined to be above a transition threshold; means for setting a respective transition inversion encoding flag associated with each data channel to indicate whether the data bits corresponding to every other cycle of the associated data channel have been inverted; means for determining a number of cycles in which data bits are set to a predetermined state on each data channel of the plurality of data channels for the predetermined number of cycles; means for inverting the data bits in the cycles of a data channel when the number of cycles in which data bits are set to the predetermined state on the data channel is above a state threshold; and means for setting a respective state inversion encoding flag associated with each data channel to indicate whether the data bits in the cycles of the associated data channel are inverted.

36. A processor-readable storage medium, comprising programming for causing a processing circuit to: determine a number of transitions on a plurality of data channels of a data bus for a predetermined number of cycles; invert data bits corresponding to every other cycle of a data channel when the number of transitions on the data channel is determined to be above a transition threshold; set a respective transition inversion encoding flag associated with each data channel to indicate whether the data bits corresponding to every other cycle of the associated data channel have been inverted; determine a number of cycles in which data bits are set to a predetermined state on each data channel of the plurality of data channels for the predetermined number of cycles; invert the data bits in the cycles of a data channel when the number of cycles in which data bits are set to the predetermined state on the data channel is above a state threshold; and set a respective state inversion encoding flag associated with each data channel to indicate whether the data bits in the cycles of the associated data channel are inverted.

37. An electronic device comprising at least one decoder, the decoder comprising: a data bus interface adapted to be coupled with a data bus to facilitate a reception of data bits; and an invertor coupled with the data bus interface, the invertor adapted to: receive, via the data bus interface, a group of data bits on a plurality of data channels; decode the group of data bits for a first encoding scheme to generate a first group of decoded data bits; and decode the first group of decoded data bits for a second encoding scheme to generate a second group of decoded data bits; wherein the invertor adapted to decode the group of data bits for the first encoding scheme comprises the invertor adapted to: identify encoding flags associated with the first encoding scheme; and invert data bits indicated by the encoding flags associated with the first encoding scheme to have been inverted.

38. The electronic device of claim 37 , wherein the invertor adapted to decode the first group of decoded data bits for the second encoding scheme comprises the invertor adapted to: identify encoding flags associated with the second encoding scheme; and invert data bits indicated by the encoding flags associated with the second encoding scheme to have been inverted.

39. The electronic device of claim 37 , wherein the first encoding scheme comprises an encoding scheme based on a number of data bits on a data channel for the group of data bits exhibiting a predetermined state.

40. The electronic device of claim 37 , wherein the first encoding scheme comprises an encoding scheme based on a number of transitions on a data channel for the group of data bits.

41. A method operational on an electronic device, comprising: receiving a group of data bits on a plurality of data channels of a data bus; decoding the group of data bits for a first encoding scheme to generate a first group of decoded data bits; and decoding the first group of decoded data bits for a second encoding scheme to generate a second group of decoded data bits; wherein decoding the group of data bits for a first encoding scheme comprises: identifying encoding flags associated with the first encoding scheme; and inverting data bits indicated by the encoding flags associated with the first encoding scheme to have been inverted.

42. The method of claim 41 , wherein decoding the first group of decoded data bits for a second encoding scheme comprises: identifying encoding flags associated with the second encoding scheme; and inverting data bits indicated by the encoding flags associated with the second encoding scheme to have been inverted.

43. The method of claim 41 , wherein decoding the group of data bits for a first encoding scheme comprises: decoding the group of data bits for an encoding scheme based on a number of data bits on a data channel exhibiting a predetermined state.

44. The method of claim 41 , wherein decoding the group of data bits for a first encoding scheme comprises: decoding the group of data bits for an encoding scheme based on a number of transitions on a data channel.

45. An electronic device, comprising: means for receiving a group of data bits on a plurality of data channels of a data bus; means for decoding the group of data bits for a first encoding scheme to generate a first group of decoded data bits; and means for decoding the first group of decoded data bits for a second encoding scheme to generate a second group of decoded data bits; wherein the means for decoding the group of data bits for a first encoding scheme comprises: means for identifying encoding flags associated with the first encoding scheme; and means for inverting data bits indicated by the encoding flags associated with the first encoding scheme to have been inverted.

46. The electronic device of claim 45 , wherein the means for decoding the first group of decoded data bits for a second encoding scheme comprises: means for identifying encoding flags associated with the second encoding scheme; and means for inverting data bits indicated by the encoding flags associated with the second encoding scheme to have been inverted.

47. The electronic device of claim 45 , wherein the first encoding scheme comprises an encoding scheme based on a number of data bits on a data channel exhibiting a predetermined state.

48. The electronic device of claim 45 , wherein the first encoding scheme comprises an encoding scheme based on a number of transitions on a data channel.

49. A processor-readable storage medium, comprising programming for causing a processing circuit to: decode a group of received data bits for a first encoding scheme to generate a first group of decoded data bits; and decode the first group of decoded data bits for a second encoding scheme to generate a second group of decoded data bits; wherein the programming for causing a processing circuit to decode the group of received data bits for the first encoding scheme comprises programming for causing a processing circuit to: identify encoding flags associated with the first encoding scheme; and invert data bits indicated by the encoding flags associated with the first encoding scheme to have been inverted.

50. The processor-readable storage medium of claim 49 , wherein the programming for causing a processing circuit to decode the first group of decoded data bits for the second encoding scheme comprises programming for causing a processing circuit to: identify encoding flags associated with the second encoding scheme; and invert data bits indicated by the encoding flags associated with the second encoding scheme to have been inverted.

51. The processor-readable storage medium of claim 49 , wherein the first encoding scheme comprises an encoding scheme based on a number of data bits on a data channel of the received data bits exhibiting a predetermined state, and the second encoding scheme comprises an encoding scheme based on a number of transitions on the data channel.

52. The processor-readable storage medium of claim 49 , wherein the first encoding scheme comprises an encoding scheme based on a number of transitions on a data channel for the received data bits, and the second encoding scheme comprises an encoding scheme based on a number of data bits on the data channel exhibiting a predetermined state.