Apparatus and Methods of Dynamic Transmit Equalization

1. An integrated circuit comprising: physical coding circuitry for encoding data bytes for transmission and decoding received data bytes; media access control circuitry for controlling link initialization and training; an interface between the physical coding and the media access control circuitry; an equalization control circuit, external to the physical coding circuitry, wherein the equalization control circuit performs dynamic transmit equalization using said interface to refine receiver coefficients during a phase where the integrated circuit operates as a slave and refine transmitter coefficients during a phase where the integrated circuit operates as a master; and a preset-to-coefficient converter in the media access control circuitry which converts transmitter preset data to transmitter coefficient data.

2. The integrated circuit of claim 1 , wherein the equalization control circuit applies preset data for equalization in an upstream component, and wherein the equalization control circuit transmits the preset data to a downstream component for application therein.

3. The integrated circuit of claim 1 , wherein the equalization control circuit refines receiver coefficients at an upstream component.

4. The integrated circuit of claim 1 , wherein the equalization control circuit refines transmitter coefficients at an upstream component.

5. The integrated circuit of claim 1 , wherein the integrated circuit comprises an upstream component, and wherein the upstream component receives commands transmitted from a downstream component, checks reception of the commands, generates acknowledgment and no acknowledgement responses based on the reception, and transmits the responses to the downstream component.

6. The integrated circuit of claim 1 , wherein the integrated circuit comprises an upstream component, and wherein the upstream component generates and transmits commands to a downstream component, receives acknowledgment and no acknowledgement responses from the downstream component, and determines a bit error rate based on the responses.

7. The integrated circuit of claim 1 , wherein the integrated circuit comprises a downstream component, and wherein the downstream component generates and transmits commands to an upstream component, receives acknowledgment and no acknowledgement responses from the upstream component, and determines a bit error rate based on the responses.

8. The integrated circuit of claim 1 , wherein the integrated circuit comprises a downstream component, and wherein the downstream component receives commands transmitted from an upstream component to the downstream component, checks reception of the commands and generate acknowledgment and no acknowledgement responses based on the reception, and transmits the responses to the upstream component.

9. The integrated circuit of claim 1 , further comprising: a training sequence transmitter in the media access control circuitry that causes transmission of commands to a training sequence receiver in another integrated circuit.

10. The integrated circuit of claim 1 , further comprising: a training sequence receiver in the media access control circuitry which receives responses from a training sequence transmitter in another integrated circuit, wherein the training sequence receiver determines a bit error rate based on the responses.

11. The integrated circuit of claim 1 , wherein the preset-to-coefficient converter outputs the transmitter coefficient data using said interface to the physical coding circuitry.

12. The integrated circuit of claim 11 , further comprising: a look-up-table in the physical coding circuitry that translates the transmitter coefficient data to analog coefficient levels.

13. The integrated circuit of claim 1 , wherein the integrated circuit comprises a field programmable gate array.

14. The integrated circuit of claim 1 , wherein the equalization control circuit and the media access control circuit comprise programmable logic which performs the dynamic transmit equalization using said interface.

15. A method of dynamic transmit equalization performed at an upstream component, the method comprising: applying preset data for equalization in the upstream component, wherein applying the preset data includes a step of converting transmitter preset data to a coefficient data signal using a preset-to-coefficient converter; transmitting said preset data for equalization to a downstream component for application therein; refining receiver coefficients at the upstream component during a first refining phase where the downstream component operates as a master and the upstream component operates as a slave; and refining transmitter coefficients at the upstream component during a second refining phase where the upstream component operates as the master and the downstream component operates as the slave.

16. The method of claim 15 , further comprising: receiving commands transmitted from the downstream component to the upstream component; checking reception of the commands and generating acknowledgment and no acknowledgement responses based on the reception; and transmitting the responses to the downstream component.

17. The method of claim 16 , wherein the refining of transmitter coefficients at the upstream component comprises: generating and transmitting commands to the downstream component; receiving acknowledgment and no acknowledgement responses from the downstream component; and determining a bit error rate based on the responses.

18. A method of dynamic transmit equalization performed at a downstream component, the method comprising: receiving preset data for equalization from an upstream component; applying the preset data for equalization in the downstream component wherein applying the preset data includes a step of converting transmitter preset data to a coefficient data signal using a preset-to-coefficient converter; refining transmitter coefficients at the downstream component during a first refining phase where the downstream component operates as a master and the upstream component operates as a slave; and refining receiver coefficients at the downstream component during a second refining phase where the upstream component operates as the master and the downstream component operates as the slave.

19. The method of claim 18 , further comprising: generating and transmitting commands to an upstream component; receiving acknowledgment and no acknowledgement responses from the upstream component; and determining a bit error rate based on the responses.

20. The method of claim 18 , further comprising: receiving commands transmitted from the upstream component to the downstream component; checking reception of the commands and generating acknowledgment and no acknowledgement responses based on the reception; and transmitting the responses to the upstream component.

21. A transceiver circuit with dynamic transmit equalization, the transceiver circuit comprising: physical coding circuitry; media access control circuitry; an interface between the physical coding circuitry and the media access control circuitry; and an equalization controller which is external to the physical coding circuitry and which performs dynamic transmit equalization using said interface to refine receiver coefficients during a phase where the integrated circuit operates as a slave and refines transmitter coefficients during a phase where the transceiver circuit operates as a master, wherein a preset-to-coefficient converter is used to convert transmit preset data to transmit coefficient data wherein the interface provides the transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry.

22. The transceiver circuit of claim 21 , wherein the media access control circuitry comprises: a training sequence transmitter that causes transmission of commands to a training sequence receiver in another transceiver circuit; and a training sequence receiver that receives responses from a training sequence receiver in the another transceiver circuit and determines a bit error rate based on the responses.

23. The transceiver circuit of claim 21 , wherein the equalization controller comprises programmable logic that performs dynamic transmit equalization using said interface.

24. The transceiver circuit of claim 21 , wherein the media access control circuitry comprises programmable logic causes transmission of commands to a training sequence receiver in another transceiver circuit, receives responses from the training sequence receiver in the other transceiver circuit, and determines a bit error rate based on the responses.