Stacked Comparator Topology for Multi-Level Signaling

1. A system for receiving a multi-level signal, the system comprising: a system input connection; a first differential pair and a second differential pair; each of the first differential pair and the second differential pair comprising a first switch and a second switch, each of the first switch and the second switch comprising a first switching terminal, a second switching terminal, and a control terminal, the second switching terminal of the first switch connected to the second switching terminal of the second switch, the control terminal of the first switch of the first differential pair connected to the system input connection, the control terminal of the first switch of the second differential pair connected to the system input connection, the first terminal of the second switch of the first differential pair connected to: the second switching terminal of the first switch of the second differential pair; and the second switching terminal of the second switch of the second differential pair. wherein: the first switching terminal of the first switch of the first differential pair is directly connected to a first terminal of a first load element; the first switching terminal of the first switch of the second differential pair is directly connected to a first terminal of a second load element; a second terminal of the first load element is directly connected to a first power supply connection; and a second terminal of the second load element is directly connected to the first power supply connection.

2. The system of claim 1 , wherein at least one of the first switch or the second switch is a semiconductor switch.

3. The system of claim 2 , wherein at least one of the first switch or the second switch is a field effect transistor (FET).

4. The system of claim 2 , wherein at least one of the first switch or the second switch is a bipolar junction transistor (BJT).

5. The system of claim 1 , wherein: the control terminal of the second switch of the first differential pair is connected to a voltage source at a first threshold voltage, and the control terminal of the Pistil second switch of the second differential pair is connected to a voltage source at a second threshold voltage.

6. The system of claim 5 , wherein the first threshold voltage is greater than the second threshold voltage.

7. The system of claim 6 , wherein: the multi-level signal comprises three adjacent levels, the first threshold voltage is half-way between a first adjacent pair of levels of the three adjacent levels, and the second threshold voltage is half-way between a second adjacent pair of levels of the three adjacent levels.

8. The system of claim 1 , wherein: the second switching terminal of the first switch of the first differential pair and the second switching terminal of the second switch of the first differential pair are connected to a first terminal of a current source; and a second terminal of the current source is connected to a second power supply connection.

9. The system of claim 8 , wherein the second power supply connection is a ground connection of a power supply.

10. The system of claim 1 , wherein: the first switching terminal of the first switch of the first differential pair is connected to a first system output connection; and the first switching terminal of the first switch of the second differential pair is connected to a second system output connection.

11. The system of claim 1 , wherein the first power supply connection is a positive connection of a power supply.

12. The system of claim 1 , wherein at least one of the first switch or the second switch is a semiconductor switch.

13. The system of claim 12 , wherein at least one of the first switch or the second switch is a field effect transistor (FET).

14. The system of claim 12 , wherein at least one of the first switch or the second switch is a bipolar junction transistor (BJT).

15. The system of claim 1 , wherein: the control terminal of the second switch of the first differential pair is connected to a voltage source at a first threshold voltage, and the control terminal of the second switch of the second differential pair is connected to a voltage source at a second threshold voltage.

16. The system of claim 15 , wherein the second threshold voltage is greater than the first threshold voltage.

17. The system of claim 16 , wherein: the multi-level signal comprises three adjacent levels, and the first threshold voltage is half-way between a first adjacent pair of levels of the three adjacent levels; and the second threshold voltage is half-way between a second adjacent pair of levels of the three adjacent levels.

18. The system of claim 1 , wherein at least one of the first load element or the second load element is a resistor.

19. The system of claim 1 , wherein at least one of the first load element or the second load element is a third switch, the third switch comprising a first switching terminal, a second switching terminal, and a control terminal, the control terminal of the third switch being connected to the first switching terminal of the third switch.

20. The system of claim 19 , wherein the third switch is a FET comprising a source terminal, a drain terminal, and a gate terminal, the drain terminal being the first switching terminal of the third switch, the source terminal being the second switching terminal of the third switch, and the gate being the control terminal of the third switch.