Tuple Construction from Data Packets

1. A method of processing a data packet, comprising: in at least one stage of a plurality of stages of a pipeline circuit, extracting a respective packet field value from the data packet; in each stage of the plurality of stages: inputting an in-process tuple into a respective tuple register; inputting a respective programmable offset value; creating in a mask register, a mask word having a subset of bits equal in number to a number of bits of a respective tuple field value and positioned in the mask word in response to the respective programmable offset value; clearing by a first circuit, bits of the in-process tuple in the respective tuple register using the subset of bits in the mask word in the mask register; inserting by a second circuit, the respective tuple field value based on the respective packet field value into the respective tuple register of the stage by replacing the cleared bits of the respective in-process tuple with the tuple field value; and in each stage of the plurality of stages except a last one of the stages, providing contents of the respective tuple register of the stage as input to a next one of the stages.

2. The method of claim 1 , further comprising, computing the respective tuple field value in the at least one stage as a function of the respective packet field value.

3. The method of claim 2 , further comprising: inputting a respective set of one or more constants to the at least one stage; and computing the respective tuple field value in the at least one stage as a function of the respective packet field value and the respective set of one or more constants.

4. The method of claim 1 , wherein: the extracting of the respective packet field value from the data packet in the at least one stage includes, extracting a respective set that includes two or more packet field values from the data packet; and the inserting of the respective tuple field value into a respective tuple register in the at least one stage includes inserting the respective tuple field value based on the respective set of two or more packet field values.

5. The method of claim 1 , further comprising, in at least one stage of the plurality of stages, inserting two tuple field values into the respective tuple register in parallel.

6. The method of claim 1 , further comprising, computing the respective tuple field value in the at least one stage as a function of the respective packet field value and at least one tuple field value of the input from a previous one of the plurality of stages.

7. The method of claim 1 , further comprising: inputting a respective set of one or more constants to the at least one stage; and computing the respective tuple field value in the at least one stage as a function of the respective packet field value, at least one tuple field value of the input from a previous one of the plurality of stages, and the respective set of one or more constants.

8. The method of claim 1 , further comprising inputting a respective programmable field size indicative of a number of bits of the respective tuple field value.

9. The method of claim 1 , wherein the creating the mask word includes: selecting a mask word having the subset of bits in right-most bits of the mask word and storing the selected mask word in the mask register; and shifting bits of the mask word a number of positions indicated by the programmable offset value.

10. A packet processing circuit, comprising: a plurality of pipeline stages, each stage including: a field extraction circuit configured to receive a data packet and configurable to extract none or a plurality of packet field values from the data packet; and a tuple construction circuit coupled to receive an input tuple, a respective programmable offset value, and each packet field value from the field extraction circuit, the tuple construction circuit configured to insert a respective tuple field value based on the received packet field values into the input tuple at a respective offset and output a tuple having the inserted respective tuple field value; wherein each tuple construction circuit includes: a first circuit configured to: create a mask word in a mask register having a subset of bits equal in number to a number of bits of the respective tuple field value and positioned in the mask word in response to the respective programmable offset value, and clear bits of the input tuple using the subset of bits in the mask word; and a second circuit configured to replace the cleared bits of the input tuple with the respective tuple field value.

11. The circuit of claim 10 , wherein each stage further comprises a computation circuit coupled to the field extraction circuit, the computation circuit configured to compute the respective tuple field value as a function of the packet field values.

12. The circuit of claim 11 , wherein each stage further comprises: a constant staging circuit coupled to the computation circuit, the constant staging circuit configured to input a respective set of one or more constants; wherein the computation circuit is configured to compute the respective tuple field value as a function of the packet field values and the respective set of one or more constants.

13. The circuit of claim 10 , wherein: the field extraction circuit is further configured to extract a respective set that includes two or more packet field values from the data packet; and the tuple construction circuit is further configured to insert the respective tuple field value based on the respective set of two or more packet field values.

14. The circuit of claim 10 , wherein the tuple construction circuit in at least one stage of the plurality of stages is further configured to insert two tuple field values into the input tuple in parallel.

15. The circuit of claim 10 , wherein each stage further comprises a computation circuit coupled to the field extraction circuit, the computation circuit configured to compute the respective tuple field value as a function of the packet field values and at least one tuple field value of the input tuple.

16. The circuit of claim 10 , further comprising: a computation circuit coupled to the field extraction circuit; and a constant staging circuit coupled to the computation circuit, the constant staging circuit configured to input a respective set of one or more constants; wherein the computation circuit is configured to compute the respective tuple field value as a function of the packet field values, at least one tuple field value of the input tuple, and the respective set of one or more constants.

17. The circuit of claim 10 , wherein each tuple construction circuit is responsive to a respective programmable tuple field size indicative of a number of bits of the respective tuple field value.

18. The packet processing circuit of claim 10 , wherein the mask circuit is further configured to: select a mask word having the subset of bits in right-most bits of the mask word; store the selected mask word in the mask register; and shift bits of the mask word a number of positions indicated by the programmable offset value.