Detection and Control of Resource Congestion by a Number of Processors

1. A system comprising: a cache memory to store data; a first processor configured to attempt to access data from the cache memory based on access requests; a second processor associated with the cache memory; and a hub controller configured to receive the access requests from the first processor, and to forward the access requests to the second processor, wherein the second processor is configured to: determine whether the data in the cache memory is accessible, transmit a negative acknowledgment back to the first processor through the hub controller when the data is not accessible, wherein the number of negative acknowledgements are counted within a time period, wherein the first processor delays attempting to access the data for a time when an average number of negative acknowledgments exceeds a threshold, and transmit a positive acknowledgment back to the first processor through the hub controller when the data is accessible.

2. The system of claim 1 , wherein: the count of negative acknowledgements is reset after the transmission of the positive acknowledgment; the count of the negative acknowledgements is incremented after the transmission of the negative acknowledgement; the first processor attempts to access the data based on another access request to access the data when a negative acknowledgment threshold has not been exceeded and after the transmission of the negative acknowledgment by the second processor; and the first processor delays attempting to access the data for a time when the negative acknowledgment threshold has been exceeded.

3. The system of claim 1 , further comprising: a shift register; and a multiplexer, wherein: the shift register includes a plurality of outputs, and at least one input, the at least one input to the shift register is coupled to the negative acknowledgments, and the plurality of outputs from the shift register are inputs to the multiplexer.

4. The system of claim 3 , wherein: a logical low is shifted into the shift register after the transmission of the positive acknowledgement, a logical high is shifted into the shift register after the transmission of the negative acknowledgment, the multiplexer includes one or more control inputs, a state of the one or more control inputs selects which input of the multiplexer will be output on an output from the multiplexer, the count of the negative acknowledgments is incremented after the transmission of the negative acknowledgment, the count of the negative acknowledgments is decremented when the output of the multiplexer has a value of one, the first processor attempts to access the data based on another access request after the second processor transmits the negative acknowledgment when a negative acknowledgment threshold has not been exceeded, and the first processor delays attempting to access the data for a time when the negative acknowledgment threshold has been exceeded.

5. The system of claim 4 , further comprising: at least one state machine, wherein after the negative acknowledgment threshold has been exceeded: receives a congestion detected signal, disables retry attempts to access the data by the first processor, and exponentially increases a delay value, wherein the delay value causes the first processor to delay attempting to access the data for the time corresponding to the delay value.

6. The system of claim 5 , wherein the at least one state machine is coupled to a plurality of different sets of congestion detection logic.

7. The system of claim 6 , wherein the one of the different sets of congestion detection logic detects an average number of number of negative acknowledgments.

8. The system of claim 7 , wherein the first processor delays attempting to access the data for the time when the average number of negative acknowledgments exceeds a threshold.

9. The system of claim 1 , further comprising: at least one state machine, wherein after the negative acknowledgment threshold has been exceeded: receives a congestion detected signal, disables retry attempts to access the data by the first processor, and exponentially increases a delay value, wherein the delay value causes the first processor to delay attempting to access the data for a time corresponding to the delay value.

10. The system of claim 1 , further comprising a positive acknowledgment counter, wherein the positive acknowledgment counter is incremented after the transmission of the positive acknowledgment.

11. The system of claim 10 , wherein the count of the negative acknowledgments is reset when the positive acknowledgment counter reaches a threshold value.

12. A method comprising: transmitting a request to access data from the cache memory by a first processor to a second processor; receiving a negative acknowledgment by the first processor when the data is not accessible, wherein the number of negative acknowledgements are counted within a time period, and the first processor delays attempting to access the data for a time when an average number of negative acknowledgments exceeds a threshold; and receiving a positive acknowledgment by the first processor when the data is accessible.

13. The method of claim 12 , further comprising: resetting the count of negative acknowledgments after the receiving the positive acknowledgment; incrementing the count of negative acknowledgments after receiving a negative acknowledgement; transmitting another access request to access the data by the first processor to the second processor after receiving the negative acknowledgment when a negative acknowledgment threshold has not been exceeded; and delaying the transmission of subsequent access requests by the first processor for the data until after a period of time when the negative acknowledgment threshold has been exceeded.

14. The method of claim 12 , after the negative acknowledgement threshold has been exceeded, further comprising: receiving a congestion detected signal, disabling retry attempts to access the data by the first processor, and exponentially increasing a delay value, wherein the delay value causes the first processor to delay attempting to access the data for the period of time corresponding to the delay value.

15. The method of claim 12 , further comprising increasing a count of positive acknowledgments when the positive acknowledgment is received by the first processor.

16. The method of claim 15 , further comprising: resetting the count of the negative acknowledgments when the positive acknowledgment count reaches a threshold value.