Conversion of a Discrete-Time Quantized Signal into a Continuous-Time, Continuously Variable Signal

1. An apparatus for converting a discrete-time quantized signal into a continuous-time, continuously variable signal, comprising: an input line for accepting full-rate samples of an input signal that are discrete in time and in value, that are separated in time by a full-rate sampling period, and that represent a signal sampled at a full-rate sampling frequency corresponding to the full-rate sampling period; a parallel signal processor having an input coupled to said input line and having a plurality of sub-rate outputs, each sub-rate output providing a different subsampling phase of a complete signal that is output by said apparatus; a first multi-bit-to-variable-level signal converter which is coupled to a first sub-rate output of the parallel signal processor and which operates at a sampling rate that is less than or equal to the full-rate sampling frequency of said input signal; a second multi-bit-to-variable-level signal converter which is coupled to a second sub-rate output of the parallel signal processor and which operates at the sampling rate; and a signal combiner coupled to an output of each of said first and second multi-bit-to-variable-level signal converters, wherein the outputs of said first and second multi-bit-to-variable-level signal converters are combined by the signal combiner, as continuous-time signals at the sampling rate of said first and second sub-rate outputs, using at least one summing operation, wherein at least one delay operation has been applied to at least one of said first sub-rate output and said second sub-rate output prior to said at least one summing operation, and wherein said at least one delay operation and said at least one summing operation together produce a filter response with a lowpass cutoff frequency that is: less than or equal to the full-rate sampling frequency of the input signal, and greater than or equal to a maximum frequency component of said input signal.

2. The apparatus according to claim 1 , wherein said at least one delay operation comprises a plurality of delay operations, and wherein each of said delay operations introduces a time-offset in an increment that is an integer multiple of the full-rate sampling period.

3. The apparatus according to claim 2 , wherein there are a total of m delay operations, and values at the output of each of said delay operations reflect subsampling at a rate which is a factor of 1 m times the full-rate sampling frequency of said input signal.

4. The apparatus according to claim 3 , wherein said filter response has a lowpass cutoff frequency that is approximately equal to 1 2 · m time the full-rate sampling frequency of said input signal.

5. An apparatus according to claim 1 , wherein at least one of said multi-bit-to-variable-level signal converters comprises at least one of: a network of weighted resistors, a network of weighted voltage sources, or a network of weighted current sources.

6. An apparatus according to claim 1 , wherein said parallel signal processor has exactly m sub-rate outputs and the sampling rate of each of said sub-rate outputs is greater than 1/m times the full-rate sampling frequency of said input signal.

7. An apparatus according to claim 6 , wherein said parallel signal processor further comprises a plurality of noise-shaped quantization circuits, each of which accepts input samples and generates output samples, wherein said output samples of said noise-shaped quantization circuits have at least one of a lower resolution or a higher sampling rate than said input samples.

8. The apparatus according to claim 1 , wherein said filter response has a lowpass cutoff frequency that is less than or equal to one-half of the full-rate sampling frequency of said input signal.

9. The apparatus according to claim 1 , wherein the maximum frequency component of said input signal is less than or equal to one-half of said full-rate sampling frequency.

10. An apparatus according to claim 1 , wherein said parallel signal processor has exactly m sub-rate outputs and the sampling rate of each of said sub-rate outputs is 1 m times the full-rate sampling frequency of said input signal.

11. The apparatus according to claim 10 , wherein a maximum frequency component of said input signal is approximately equal to 1 2 · m times the full-rate sampling frequency of said input signal.

12. An apparatus according to claim 1 , wherein said at least one delay operation introduces an offset in time via digital resampling on different phases of a sub-rate clock.

13. The apparatus according to claim 1 , wherein said at least one delay operation introduces an offset in time via signal propagation through a continuous-time delay line.

14. The apparatus according to claim 13 , wherein said delay line is entirely passive.

15. The apparatus according to claim 13 , wherein said delay line includes an active component.

16. The apparatus according to claim 1 , wherein all discrete-time components of said apparatus operate at a maximum switching rate which is less than the full-rate sampling frequency of said input signal.

17. The apparatus according to claim 1 , wherein said filter response is approximately a sinc function.

18. The apparatus according to claim 1 , wherein each of the outputs from said first and second multi-bit-to-variable-level signal converters, which is coupled to said signal combiner, has been shaped according to a non-rectangular window, and the filter response has an upper stopband with attenuation greater than a sinc function.

19. The apparatus according to claim 1 , wherein said first and second sub-rate outputs are coupled to inputs of said signal combiner and combined within said signal combiner without upsampling.

20. The apparatus according to claim 1 , wherein said at least one delay operation and said at least one summing operation together implement an operation that comprises a moving-average summation.

21. The apparatus according to claim 1 , wherein said parallel signal processor performs estimation and mitigation of at least one of clock jitter or sample-rate skew.

22. The apparatus according to claim 21 , wherein said parallel signal processor dynamically resamples a signal provided to the input of said parallel signal processor to reflect sampling skew that is approximately equal and opposite to sampling skew introduced by imperfections in said at least one delay operation.

23. The apparatus according to claim 22 , wherein resampling is dynamically adjusted to minimize a level of at least one spurious signal present in the complete signal that is output by said apparatus.