Method of Allocating Resources for Transmitting Uplink Signal in Mimo Wireless Communication System and Apparatus Thereof

1. A method for transmitting an uplink signal using L layers at a terminal in a multiple-input multiple-output (MIMO) wireless communication system, the method comprising: generating, by the terminal, modulation symbols by modulating output bit sequences of an interleaver matrix by a unit of log 2 Q bits, wherein Q is a modulation order, and wherein each of the output bit sequences has a size of L*log 2 Q bits and L is a number of layers; mapping, by the terminal, the modulation symbols to the L layers; and transmitting, by the terminal, the modulation symbols by using the L layers.

2. The method according to claim 1 , wherein the output bit sequences are generated by reading out entries of the interleaver matrix, column by column.

3. The method according to claim 1 , wherein if a number of modulation symbols per layer is given by H and a number of columns of the interleaver matrix is given by C, a number of rows R of the interleaver matrix is defined by Equation 1 shown below: H · L · log 2 ⁢ Q C . 〈 Equation ⁢ ⁢ 1 〉

4. The method according to claim 3 , wherein the interleaver matrix is represented by Equation 2 shown below: [ g 0 g 1 … g C - 1 g C g C + 1 … g 2 ⁢ C - 1 ⋮ ⋮ ⋱ ⋮ g ( R ′ - 1 ) · C g ( R ′ - 1 ) · C + 1 … g R ′ · C - 1 ] , 〈 Equation ⁢ ⁢ 2 〉 R ′ = R L · log 2 ⁢ Q wherein and g k is a vector defined by L·log 2 Q rows.

6. A terminal apparatus of a multiple-input multiple-output (MIMO) wireless communication system, the terminal apparatus comprising: a processor configured to: generate modulation symbols by modulating output bit sequences of an interleaver matrix by a unit of log 2 Q bits, wherein Q is a modulation order, and wherein each of the output bit sequences has a size of L·log 2 Q bits and L is a number of layers, and map the modulation symbols to the L layers; and a transmission module configured to transmit the modulation symbols by using the L layers.

7. The terminal apparatus according to claim 6 , wherein the processor is configured to generate the output bit sequences by reading out entries of the interleaver matrix, column by column.

8. The terminal apparatus according to claim 6 , wherein if a number of modulation symbols per layer is given by H and a number of columns of the interleaver matrix is given by C, a number of rows R of the interleaver matrix is defined by Equation 1 shown below: H · L · log 2 ⁢ Q C . 〈 Equation ⁢ ⁢ 1 〉

9. The terminal apparatus according to claim 8 , wherein the interleaver matrix is represented by Equation 2 shown below: [ g 0 g 1 … g C - 1 g C g C + 1 … g 2 ⁢ C - 1 ⋮ ⋮ ⋱ ⋮ g ( R ′ - 1 ) · C g ( R ′ - 1 ) · C + 1 … g R ′ · C - 1 ] , 〈 Equation ⁢ ⁢ 2 〉 wherein R ′ = R L · log 2 ⁢ Q and g k is a vector defined by L·log 2 Q rows.