Performing Quotient Selection for a Carry-Save Division Operation

1. In an integrated circuit (IC), a method for performing quotient selection for a carry-save division operation, wherein the carry-save division operation divides a dividend, R, by a divisor, D, to produce an approximation of a quotient, Q=R/D, the method comprising: circuitry in the IC approximating Q by iteratively selecting and performing an operation for each iteration of the carry-save division operation, wherein the operation for a given iteration is selected based on a set of partial sum bits of a partial remainder in carry-save form (rs) and a set of partial carry bits of a partial remainder in carry-save form (rc); wherein the operation for the given iteration is selected from a set of operations that comprises: a “2X* operation” in which an inverting shift circuit in the IC performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit 0 is retired; an “S1 & 2X* operation” in which a carry-select addition circuit in the IC subtracts the divisor from rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit 1 is retired; an “S2 & 2X* operation” in which the carry-select addition circuit subtracts twice the divisor from rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit 2 is retired; an “A1 & 2X* operation” in which the carry-select addition circuit adds the divisor to rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit −1 is retired; and an “A2 & 2X* operation” in which the carry-select addition circuit adds twice the divisor to rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit −2 is retired.

2. The computer-implemented method of claim 1 , wherein q*D+2 −k *r=R, where q is the quotient computed after iteration k and the variable r is the partial remainder computed after iteration k; wherein the partial remainder r is in redundant carry-save form such that r=rs+rc; wherein K defines the ranges for R and D such that R lies in [2 K , 2 K+1 ) and D lies in [2 K , 2 K+1 ); and wherein performing the carry-save division operation comprises selecting from the set of operations during each iteration of the carry-save division operation based on the values of rs and rc for each given iteration.

3. The computer-implemented method of claim 2 , wherein the set of five operations available for each iteration completely cover the possible combinations of rs and rc and facilitate substantially reducing the complexity of the quotient selection logic circuitry for the carry-save division operation.

4. The computer-implemented method of claim 2 , wherein the method further comprises receiving a first signal and a second signal that are used to select the operation for the given iteration of the carry-save division operation; wherein the first signal comprises two bits that select a multiple of D for the carry-save addition operation; and wherein the second signal comprises one bit that selects between a result for the carry-save addition operation and a result for the 2X* operation.

5. The computer-implemented method of claim 4 , wherein rs[0] is the most significant bit of rs,rs[1] is the second-most significant bit of rs, rc[0] is the most significant bit of rc, and rc[1] is the second-most significant bit of rc; wherein calculating the first signal comprises determining the values for (rs[0]· rs[1] · rc[1] )|( rs[0] ·rs[1]·rc[1]) and rs[0] ; and wherein calculating the second signal comprises determining the value for rs[0]⊕rc[0].

6. The computer-implemented method of claim 5 , wherein the latency for each given iteration comprises: the delay associated with a four-input multiplexer that multiplexes the values −2D, 2D, −D, and D; the delay associated with a carry-save adder that operates upon the output of the four-input multiplexer; the delay associated with a two-input multiplexer that multiplexes the output of the carry-save adder and the result of the 2X* operation; the delay associated with the quotient selection logic that calculates the first signal and the second signal; and the delay associated with a set of flip-flops that store the intermediate results for the given iteration.

7. The computer-implemented method of claim 2 , wherein the method further comprises scaling the divisor to match the range of a divider that is performing the carry-save division operation.

8. The computer-implemented method of claim 2 , wherein a divider that is performing the carry-save division operation is a variable-iteration divider; and wherein the set of operations further comprises a “4X* operation” that performs a left shift of rs and rc, performs a second left shift of rs and rc, inverts the most-significant bit of rs and rc, and then retires two quotient digits 00.

9. The computer-implemented method of claim 8 , wherein the set of operations further comprises a “4X operation” that performs a left shift of rs and rc, performs a second left shift of rs and rc, and then retires two quotient digits 00.

10. The computer-implemented method of claim 8 , wherein the set of operations further comprises an “8X* operation” that performs a left shift of rs and rc, performs a second left shift of rs and rc, performs a third left shift of rs and rc, inverts the most-significant bit of rs and rc, and then retires three quotient digits 000.

11. The computer-implemented method of claim 10 , wherein the set of operations further comprises a “4X operation” that performs a left shift of rs and rc, performs a second left shift of rs and rc, and then retires two quotient digits 00.

12. The computer-implemented method of claim 8 , wherein the set of operations further comprises: an “A1 & 4X* operation” that performs the A1 & 2X* operation followed by the 2X* operation, thereby first retiring a quotient digit −1 and then retiring a quotient digit 0; an “A2 & 4X* operation” that performs the A2 & 2X* operation followed by the 2X* operation, thereby first retiring a quotient digit −2 and then retiring a quotient digit 0; an “S1 & 4X* operation” that performs the S1 & 2X* operation followed by the 2X* operation, thereby first retiring a quotient digit 1 and then retiring a quotient digit 0; and an “S2 & 4X* operation” that performs the S2 & 2X* operation followed by the 2X* operation, thereby first retiring a quotient digit 2 and then retiring a quotient digit 0.

13. The computer-implemented method of claim 9 , wherein the set of operations further comprises: an “A1 & 4X* operation” that performs the A1 & 2X* operation followed by the 2X* operation, thereby first retiring a quotient digit −1 and then retiring a quotient digit 0; an “A2 & 4X* operation” that performs the A2 & 2X* operation followed by the 2X* operation, thereby first retiring a quotient digit −2 and then retiring a quotient digit 0; an “S1 & 4X* operation” that performs the S1 & 2X* operation followed by the 2X* operation, thereby first retiring a quotient digit 1 and then retiring a quotient digit 0; and an “S2 & 4X* operation” that performs the S2 & 2X* operation followed by the 2X* operation, thereby first retiring a quotient digit 2 and then retiring a quotient digit 0.

14. The computer-implemented method of claim 11 , wherein the set of operations further comprises: an “A1 & 4X* operation” that performs the A1 & 2X* operation followed by the 2X* operation, thereby first retiring a quotient digit −1 and then retiring a quotient digit 0; an “A2 & 4X* operation” that performs the A2 & 2X* operation followed by the 2X* operation, thereby first retiring a quotient digit −2 and then retiring a quotient digit 0; an “S1 & 4X* operation” that performs the S1 & 2X* operation followed by the 2X* operation, thereby first retiring a quotient digit 1 and then retiring a quotient digit 0; and an “S2 & 4X* operation” that performs the S2 & 2X* operation followed by the 2X* operation, thereby first retiring a quotient digit 2 and then retiring a quotient digit 0.

15. A carry-save division circuit, wherein the carry-save division circuit divides a dividend, R, by a divisor, D, to produce an approximation of a quotient, Q=R/D, comprising: a division circuit that comprises a carry-save addition circuit, an inverting shift circuit, and a quotient selection logic circuit; wherein the division circuit is configured to perform a carry-save division operation that approximates Q by iteratively selecting and performing an operation for each iteration of the carry-save division operation, wherein the operation for a given iteration is selected based on a set of partial sum bits of a partial remainder in carry-save form (rs) and a set of partial carry bits of a partial remainder in carry-save form (rc); and wherein the operation for the given iteration is selected from a set of operations that comprises: a “2X* operation” in which the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit 0 is retired; an “S1 & 2X* operation” in which the carry-select addition circuit subtracts the divisor from rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit 1 is retired; an “S2 & 2X* operation” in which the carry-select addition circuit subtracts twice the divisor from rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit 2 is retired; an “A1 & 2X* operation” in which the carry-select addition circuit adds the divisor to rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit −1 is retired; and an “A2 & 2X* operation” in which the carry-select addition circuit adds twice the divisor to rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit −2 is retired.

16. The carry-save division circuit of claim 15 , wherein q*D+2 −k *r=R, where q is the quotient computed after iteration k and the variable r is the partial remainder computed after iteration k; wherein the partial remainder r is in redundant carry-save form such that r=rs+rc; wherein K defines the ranges for R and D such that R lies in [2 K , 2 K+1 ) and D lies in [2K, 2 K+1 ); and wherein performing the carry-save division operation comprises selecting from the set of operations during each iteration of the carry-save division operation based on the values of rs and rc for each given iteration.

17. The carry-save division circuit of claim 16 , wherein the set of five operations available for each iteration completely cover the possible combinations of rs and rc and facilitate substantially reducing the complexity of the quotient selection logic circuit.

18. The carry-save division circuit of claim 16 , wherein the quotient selection logic circuit generates a first signal and a second signal that are used to select the operation for a given iteration of the carry-save division operation; wherein the first signal comprises two bits that select a multiple of D for the carry-save addition operation; and wherein the second signal comprises one bit that selects between a result for the carry-save addition operation and a result for the 2X* operation.

19. The carry-save division circuit of claim 18 , wherein rs[0] is the most significant bit of rs, rs[1] is the second-most significant bit of rs, rc[0] is the most significant bit of rc, and rc[1] is the second-most significant bit of rc; wherein the quotient selection logic circuit is configured to calculate the first signal by determining the values for (rs[0]· rs[1] · rc[1] )|( rs[0] ·rs[1]·rc[1]) and rs[0] ; and wherein the quotient selection logic circuit is configured to calculate the second signal by determining the value for rs[0]⊕rc[0].

20. A non-transitory computer-readable storage medium storing instructions that when executed by an integrated circuit (IC) cause the IC to perform a method for performing quotient selection for a carry-save division operation, wherein the carry-save division operation divides a dividend, R, by a divisor, D, to produce an approximation of a quotient, Q=R/D, the method comprising: circuitry in the IC approximating Q by iteratively selecting and performing an operation for each iteration of the carry-save division operation, wherein the operation for a given iteration is selected based on a set of partial sum bits of a partial remainder in carry-save form (rs) and a set of partial carry bits of a partial remainder in carry-save form (rc); wherein the operation for the given iteration is selected from a set of operations that comprises: a “2X* operation” in which an inverting shift circuit in the IC performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit 0 is retired; an “S1 & 2X* operation” in which a carry-select addition circuit in the IC subtracts the divisor from rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit 1 is retired; an “S2 & 2X* operation” in which the carry-select addition circuit subtracts twice the divisor from rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit 2 is retired; an “A1 & 2X* operation” in which the carry-select addition circuit adds the divisor to rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit −1 is retired; and an “A2 & 2X* operation” in which the carry-select addition circuit adds twice the divisor to rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit −2 is retired.