Circuit Arrangement of Gate Side Fan Out Area

1. A circuit arrangement of a gate side fan out area, comprising: a first circuit module, a second circuit module, a third circuit module and a first transistor; a gate of the first transistor is coupled to a first input end, a drain and a source of the first transistor are respectively coupled to a second input end and a N th gate scan line, and N is a nature number; a first end of the first circuit module is coupled to the first input end, a second end of the first circuit module is coupled to the second input end, and a third end of the first circuit module is coupled to the N+1 th gate scan line; a first end and a second end of the second circuit module are coupled to the second input end, and a third end of the second circuit module is coupled to the N th gate scan line; a first end and a second end of the third circuit module are coupled to the second input end, and a third end of the third circuit module is coupled to the N+1 th gate scan line; a periodic square wave is inputted to the first input end, and a gate scanning signal is inputted to the second input end, and a period of the periodic square wave is twice a scanning period of the gate scanning signal; the first circuit module is in off state between the second end and the third end when an input voltage to the first end of the first circuit module is equal to a first amplitude voltage of the periodic square wave; the first circuit module is in on state between the second end and the third end when an input voltage to the second end of the first circuit module is equal to a second amplitude voltage of the periodic square wave; the second circuit module is in off state between the second end and the third end when an input voltage to the first end of the second circuit module is equal to a first amplitude voltage of the periodic square wave; the second circuit module is in on state between the second end and the third end when an input voltage to the second end of the second circuit module is equal to a second amplitude voltage of the periodic square wave; the third circuit module is in off state between the second end and the third end when an input voltage to the first end of the third circuit module is equal to a first amplitude voltage of the periodic square wave; the third circuit module is in on state between the second end and the third end when an input voltage to the first end of the third circuit module is equal to a second amplitude voltage of the periodic square wave.

2. The circuit arrangement of the gate side fan out area according to claim 1 , wherein the first transistor is a NMOS transistor.

3. The circuit arrangement of the gate side fan out area according to claim 1 , wherein circuit arrangements of the first circuit module, the second circuit module and the third circuit module are the same.

4. The circuit arrangement of the gate side fan out area according to claim 1 , wherein the first circuit module comprises a second NMOS transistor and a third NMOS transistor; a gate of the second NMOS transistor is employed as the first end of the first circuit module, a source and a drain of the second NMOS transistor are respectively inputted with the first amplitude voltage and the second amplitude voltage; a gate of the third NMOS transistor is inputted with the first amplitude voltage, and a source and a drain of the third NMOS transistor are respectively employed as the second end and the third end of the first circuit module.

5. The circuit arrangement of the gate side fan out area according to claim 1 , wherein the second circuit module comprises a second NMOS transistor and a third NMOS transistor; a gate of the second NMOS transistor is employed as the first end of the first circuit module, a source and a drain of the second NMOS transistor are respectively inputted with the first amplitude voltage and the second amplitude voltage; a gate of the third NMOS transistor is inputted with the first amplitude voltage, and a source and a drain of the third NMOS transistor are respectively employed as the second end and the third end of the second circuit module.

6. The circuit arrangement of the gate side fan out area according to claim 1 , wherein the third circuit module comprises a second NMOS transistor and a third NMOS transistor; a gate of the second NMOS transistor is employed as the first end of the first circuit module, a source and a drain of the second NMOS transistor are respectively inputted with the first amplitude voltage and the second amplitude voltage; a gate of the third NMOS transistor is inputted with the first amplitude voltage, and a source and a drain of the third NMOS transistor are respectively employed as the second end and the third end of the third circuit module.

7. The circuit arrangement of the gate side fan out area according to claim 1 , wherein the first amplitude voltage is 3.3V.

8. The circuit arrangement of the gate side fan out area according to claim 1 , wherein the second amplitude voltage is −7V.

9. The circuit arrangement of the gate side fan out area according to claim 1 , wherein the gate scanning signal is from a G-COF.

10. The circuit arrangement of the gate side fan out area according to claim 1 , wherein the gate scanning signal is from a gate driving circuit.

11. A circuit arrangement of a gate side fan out area, comprising: a first circuit module, a second circuit module, a third circuit module and a first transistor; a gate of the first transistor is coupled to a first input end, a drain and a source of the first transistor are respectively coupled to a second input end and a N th gate scan line, and N is a nature number; a first end and a second end of the second circuit module are coupled to the second input end, and a third end of the second circuit module is coupled to the N th gate scan line; a first end and a second end of the third circuit module are coupled to the second input end, and a third end of the third circuit module is coupled to the N+1 th gate scan line; a periodic square wave is inputted to the first input end, and a gate scanning signal is inputted to the second input end, and a period of the periodic square wave is twice a scanning period of the gate scanning signal; the first circuit module is in off state between the second end and the third end when an input voltage to the first end of the first circuit module is equal to a first amplitude voltage of the periodic square wave; the first circuit module is in on state between the second end and the third end when an input voltage to the second end of the first circuit module is equal to a second amplitude voltage of the periodic square wave; the second circuit module is in off state between the second end and the third end when an input voltage to the first end of the second circuit module is equal to a first amplitude voltage of the periodic square wave; the second circuit module is in on state between the second end and the third end when an input voltage to the second end of the second circuit module is equal to a second amplitude voltage of the periodic square wave; the third circuit module is in off state between the second end and the third end when an input voltage to the first end of the third circuit module is equal to a first amplitude voltage of the periodic square wave; the third circuit module is in on state between the second end and the third end when an input voltage to the first end of the third circuit module is equal to a second amplitude voltage of the periodic square wave; wherein the first transistor is a NMOS transistor; wherein circuit arrangements of the first circuit module, the second circuit module and the third circuit module are the same; wherein the first circuit module comprises a second NMOS transistor and a third NMOS transistor; a gate of the second NMOS transistor is employed as the first end of the first circuit module, a source and a drain of the second NMOS transistor are respectively inputted with the first amplitude voltage and the second amplitude voltage; a gate of the third NMOS transistor is inputted with the first amplitude voltage, and a source and a drain of the third NMOS transistor are respectively employed as the second end and the third end of the first circuit module; wherein the second circuit module comprises a second NMOS transistor and a third NMOS transistor; a gate of the second NMOS transistor is employed as the first end of the first circuit module, a source and a drain of the second NMOS transistor are respectively inputted with the first amplitude voltage and the second amplitude voltage; a gate of the third NMOS transistor is inputted with the first amplitude voltage, and a source and a drain of the third NMOS transistor are respectively employed as the second end and the third end of the second circuit module; wherein the third circuit module comprises a second NMOS transistor and a third NMOS transistor; a gate of the second NMOS transistor is employed as the first end of the first circuit module, a source and a drain of the second NMOS transistor are respectively inputted with the first amplitude voltage and the second amplitude voltage; a gate of the third NMOS transistor is inputted with the first amplitude voltage, and a source and a drain of the third NMOS transistor are respectively employed as the second end and the third end of the third circuit module.

12. The circuit arrangement of the gate side fan out area according to claim 11 , wherein the first amplitude voltage is 3.3V.

13. The circuit arrangement of the gate side fan out area according to claim 11 , wherein the second amplitude voltage is −7V.

14. The circuit arrangement of the gate side fan out area according to claim 11 , wherein the gate scanning signal is from a G-COF.

15. The circuit arrangement of the gate side fan out area according to claim 11 , wherein the gate scanning signal is from a gate driving circuit.