Legal claims defining the scope of protection, as filed with the USPTO.
1. A power on circuit connected between a video graphics array (VGA) connector of a display and a super input output (SIO) chip of a motherboard, the power on circuit comprising: a first capacitor; a first resistor, a second resistor, and a third resistor; a first electronic switch comprising a first terminal connected to a serial data line (SDA) pin of the VGA connector, a second terminal connected to a power supply through a first resistor, and a third terminal grounded; a second electronic switch comprising a first terminal connected to the second terminal of the first electronic switch, a second terminal connected to the power supply, and a third terminal; a timer comprising a power pin connected to the third terminal of the second electronic switch, a trigger pin connected to the third terminal of the second electronic switch through the second resistor and the third resistor in that order, a reset pin connected to the power pin, a control pin grounded through the first capacitor, a threshold pin connected to the trigger pin, a discharge pin connected to a node between the second resistor and the third resistor, and an output pin; a third electronic switch comprising a first terminal connected to the output pin of the timer, a second terminal connected to the SIO chip, and a third terminal; and a fourth electronic switch comprising a first terminal connected to the third terminal of the second electronic switch, a second terminal connected to the third terminal of the third electronic switch, and a third terminal grounded; wherein in response to a power button of the display being pressed to turn on the display, the SDA pin of the VGA connector outputs a high level signal, the first electronic switch is turned on, the second electronic switch is turned on, the fourth electronic switch is turned on, the output pin of the timer outputs a periodic pulse signal; and wherein in response to the pulse signal outputted from the output pin of the timer being at a high level, the third electronic switch is turned on, the SIO chip receives a low level signal from the fourth and third electronic switches, the motherboard is turned on.
2. The power on circuit of claim 1 , further comprising a fifth electronic switch, wherein the fifth electronic switch comprises a first terminal connected to a power supply unit (PSU) to receive a power good signal from the PSU, a second terminal connected to the first terminal of the fourth electronic switch, and a third terminal grounded; and wherein in response to the motherboard being turned on, the power good signal turns to a high level, the fifth electronic switch is turned on, the fourth electronic switch is turned off, the SIO chip receives a high level signal from the second terminal of the third electronic switch, the motherboard begins to operate.
3. The power on circuit of claim 2 , further comprising a fourth resistor, wherein the first terminal of the fifth electronic switch is connected to the PSU through the fourth resistor.
4. The power on circuit of claim 3 , wherein the fifth electronic switch is an npn bipolar junction transistor (BJT), and the first terminal, the second terminal, and the third terminal of the fifth electronic switch are respectively a base, a collector, and an emitter of the npn BJT.
5. The power on circuit of claim 1 , further comprising a fifth resistor and a sixth resistor, wherein the first terminal of the first electronic switch is connected to the SDA pin of the VGA connector through the fifth resistor, and grounded through the sixth resistor.
6. The power on circuit of claim 1 , wherein the first electronic switch is an npn bipolar junction transistor (BJT), and the first terminal, the second terminal, and the third terminal of the first electronic switch are respectively a base, a collector, and an emitter of the npn BJT.
7. The power on circuit of claim 1 , further comprising a seventh resistor, wherein the first terminal of the third electronic switch is connected to the output pin of the timer through the seventh resistor.
8. The power on circuit of claim 1 , wherein the third electronic switch is an npn bipolar junction transistor (BJT), and the first terminal, the second terminal, and the third terminal of the third electronic switch are respectively a base, a collector, and an emitter of the npn BJT.
9. The power on circuit of claim 1 , further comprising an eighth resistor, wherein the first terminal of the fourth electronic switch is connected to the third terminal of the second electronic switch through the eighth resistor.
10. The power on circuit of claim 1 , wherein the second electronic switch is a pnp bipolar junction transistor (BJT), and the first terminal, the second terminal, and the third terminal of the second electronic switch are respectively a base, an emitter, and a collector of the pnp BJT; and wherein the fourth electronic switch is an npn BJT, and the first terminal, the second terminal, and the third terminal of the fourth electronic switch are respectively a base, a collector, and an emitter of the npn BJT.
11. The power on circuit of claim 1 , further comprising a first diode, a second diode, and a second capacitor, wherein the first diode comprises an anode connected to the trigger pin of the timer and grounded through the second capacitor, and a cathode connected to the discharge pin of the timer through the second resistor; and wherein the second diode comprises an anode connected to the node between the second resistor and the third resistor, and a cathode connected to the anode of the first diode.
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April 19, 2016
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