Performance of Emerging Applications in a Virtualized Environment Using Transient Instruction Streams

1. A non-transitory computer-usable medium embodying computer program code, the computer program code comprising computer executable instructions configured for: inserting a transient hint into an instruction request stream to indicate a transient instruction, the transient instruction comprising an infrequently executed instruction, the infrequently executed instruction corresponding to an instruction in which a number of processor cycles between accessing the instruction would cause the instruction to pollute a cache; inserting a non-transient hint into the instruction request stream to indicate a non-transient instruction; processing the instruction request stream to identify the transient instruction; setting a transient instruction bit in a Special Purpose Register (SPR) when the transient instruction is identified; storing the transient instruction in a high-level cache; processing the transient instruction, wherein the transient instruction is not stored in a lower-level cache; resetting the transient instruction bit when a non-transient hint is detected; and, processing a non-transient instruction based upon transient instruction bit being reset, the processing including storing the non-transient instruction in the lower-level cache.

2. The computer usable medium of claim 1 , wherein the transient hint is inserted in a Branch-and-Link (BRL) instruction.

3. The computer usable medium of claim 1 , wherein the non-transient hint is inserted into a Return (RET) instruction.

4. The computer usable medium of claim 3 , wherein the transient bit in the SPR is reset when the RET instruction containing the non-transient hint is processed.

5. The computer usable medium of claim 4 , wherein subsequent instructions are processed as non-transient instructions and are written to the lower-level cache after the transient bit is reset.

6. The computer usable medium of claim 1 , wherein subsequent instructions are processed as non-transient instructions and are written to the lower-level cache after the transient bit is reset.

7. The computer usable medium of claim 1 , wherein the transient instruction is a fetch instruction.

8. The computer usable medium of claim 1 , wherein the transient instruction is a prefetch instruction.

9. A system comprising: a processor having a high level cache; a low level cache; a data bus coupled to the processor and the low level cache; and memory, coupled to the processor through the data bus, for storing computer readable code to be processed by the processor for: inserting a transient hint into an instruction request stream to indicate a transient instruction, the transient instruction comprising an infrequently executed instruction, the infrequently executed instruction corresponding to an instruction in which a number of processor cycles between accessing the instruction would cause the instruction to pollute a cache; inserting a non-transient hint into the instruction request stream to indicate a non-transient instruction; processing the instruction request stream to identify the transient instruction; setting a transient instruction bit in a Special Purpose Register (SPR) when the transient instruction is identified; storing the transient instruction in the high-level cache; processing the transient instruction, wherein the transient instruction is not stored in the lower-level cache; resetting the transient instruction bit when a non-transient hint is detected; and, processing a non-transient instruction based upon transient instruction bit being reset, the processing including storing the non-transient instruction in the lower-level cache.

10. The system of claim 9 , wherein the processor inserts the transient hint in a Branch-and-Link (BRL) instruction.

11. The system of claim 9 , wherein the non-transient hint is inserted into a Return (RET) instruction.

12. The system of claim 11 , wherein the transient bit in the SPR is reset when the RET instruction containing the non-transient hint is processed.

13. The system of claim 12 , wherein subsequent instructions are processed as non-transient instructions and are written to the lower-level cache after the transient bit is reset.

14. The system of claim 9 , wherein an instruction is written in the high-level cache and the low-level cache if the lower-level cache is not inclusive of the high-level cache.