System and Method for Calibration of Serial Links Using a Serial-To-Parallel Loopback

1. A method for calibrating communication, said method comprising: sending serialized data over a serial interface from a first location; receiving parallel data via a parallel interface from a second location, wherein said parallel data comprises a deserialized representation of said serialized data, wherein said parallel data is looped back to said first location via said parallel interface; comparing said parallel data received from said second location and said serialized data sent from said first location for a match thereof; and calibrating said serial interface by adjusting said sending of said serialized data until said comparing detects said match.

2. The method as described in claim 1 wherein said adjusting said sending comprising adjusting timing of said sending of said serialized data.

3. The method as described in claim 1 wherein said adjusting said sending comprising adjusting framing of said serialized data.

4. The method as described in claim 1 wherein a plurality of parallel links coupled to said parallel interface is uncalibrated and said serialized data is received via each of said parallel links at a frequency lower than a frequency of a serial link coupled to said serial interface.

5. The method as described in claim 1 wherein said serial interface is operable for sending an address to a memory component.

6. The method as described in claim 1 wherein said parallel interface is operable for receiving data from a memory component.

7. The method as described in claim 1 wherein said sending said serialized data and said receiving said parallel data are performed by a memory controller.

8. The method as described in claim 1 further comprising: determining whether an additional serial link is operable for calibration.

9. A system for calibrating communication over a serial link, said system comprising: a serialization module operable for serializing data and transmitting serial data over said serial link from a first location; a parallel interface module operable for receiving parallel data over a plurality of parallel links from a second location, wherein said parallel data comprises a deserialized representation of said serial data; a comparison module operable for comparing said serial data sent via said serialization module with said parallel data received via said parallel interface module; and a training module operable for configuring timing of transmission of data over said serial link based on results from said comparison module.

10. The system as described in claim 9 wherein said training module is further operable to configure framing of transmission of data over said serial link.

11. The system as described in claim 9 wherein said serial link is an address link.

12. The system as described in claim 9 wherein each parallel link of said plurality of parallel links is a data link.

13. The system as described in claim 9 wherein said serialization module is operable for serializing address data.

14. The system as described in claim 9 wherein said serialization module and said parallel interface module are coupled to a memory component.

15. The system as described in claim 14 wherein said memory component is a memory buffer.

16. A system comprising: a memory controller comprising a serial interface and a parallel interface, wherein said memory controller is operable to send serialized data from a first location over said serial interface, and wherein said memory controller is further operable to configure framing and timing of said serialized data sent over said serial interface based on corresponding parallel data received via said parallel interface from a second location; and a memory component coupled to said memory controller via said serial interface and said parallel interface, wherein said memory component is operable to deserialize data received via said serial interface and operable to loopback said deserialized data via said parallel interface.

17. The system as described in claim 16 wherein said serial interface is coupled to an address portion of said memory component.

18. The system as described in claim 16 wherein said parallel interface is coupled to a data portion of said memory component.

19. The system as described in claim 16 wherein said memory component is a memory buffer.

20. The system as described in claim 16 wherein said memory controller is operable to periodically configure framing and timing of data sent over said serial interface.