Transactional Memory That Supports a Get from One of a Set of Rings Command

1. A transactional memory, comprising: a memory unit that stores a first ring and a second ring, wherein the first ring includes a first tail buffer and a first head buffer, and wherein the second ring includes a second tail buffer and a second head buffer; and a ring buffer control circuit that receives a get from one of a set of rings command onto the transactional memory from a bus, wherein the ring buffer control circuit does not have an instruction counter that it uses to fetch instructions from any memory, wherein the ring buffer control circuit comprises: a memory access portion coupled to read from and write to the memory unit; and a ring operation portion, wherein the ring operation portion: 1) maintains a first head pointer so that the first head pointer points to the first head buffer of the first ring, maintains a first tail pointer so that the first tail pointer points to the first tail buffer of the first ring, maintains a second head pointer so that the second head pointer points to the second head buffer of the second ring, and maintains a second tail pointer so that the second tail pointer points to the second tail buffer of the second ring, 2) determines if the first ring is empty, 3) determines if the second ring is empty, 4) if the first ring is determined not be empty then the ring operation portion supplies a first address to the memory access portion such that the memory access portion uses the first address to read a first value out of the head buffer of the first ring, whereas if the first ring is determined to be empty and the second ring is determined not to be empty then the ring operation portion supplies a second address to the memory access portion such that the memory access portion uses the second address to read a second value out of the head buffer of the second ring.

2. The transactional memory of claim 1 , wherein the ring buffer control circuit is a pipeline, wherein the ring operation portion is a stage of the pipeline, and wherein the memory access portion comprises a plurality of other stages of the pipeline.

3. The transactional memory of claim 2 , wherein the pipeline is clocked by a clock signal, and wherein the ring operation portion processes a different command each cycle of the clock signal.

4. The transactional memory of claim 1 , wherein if both the first and second rings are determined to be empty then neither the first head buffer of the first ring nor the second head buffer of the second ring is read and the memory access portion outputs an error message that is communicated from the transactional memory to the bus.

5. The transactional memory of claim 1 , wherein the ring operation portion uses the first head pointer and the first tail pointer to determine if the first ring is empty, and wherein the ring operation portion uses the second head pointer and the second tail pointer to determine if the second ring is empty.

6. The transactional memory of claim 1 , wherein the ring operation portion includes a first and a second count of entries value, wherein the ring operation portion compares the first count of entries value with a first preset value to determine if the first ring is empty, and wherein the ring operation portion compares the second count of entries value with a second preset value to determine if the second ring is empty.

7. A method comprising: (a) storing a first ring of buffers in a memory unit of a transactional memory, wherein the first ring of buffers includes a first head buffer and a first tail buffer; (b) storing a second ring of buffers in the memory unit, wherein the second ring of buffers includes a second head buffer and a second tail buffer; (c) maintaining a first head pointer so that the first head pointer points to the first head buffer of the first ring, maintaining a first tail pointer so that the first tail pointer points to the first tail buffer of the first ring, maintaining a second head pointer so that the second head pointer points to the second head of the second ring, and maintaining a second tail pointer so that the second tail pointer points to the second tail of the second ring, wherein the first head pointer, the first tail pointer, the second head pointer and the second tail pointers are stored in a first stage of a pipeline of the transactional memory; (d) receiving a get from one of a set of rings command from a bus and onto the transactional memory; (e) in the first stage of the pipeline determining if the first ring is empty; (f) in the first stage of the pipeline determining if the second ring is empty; and (g) if the first ring is empty then using the first tail pointer to read a first value from the first ring, whereas if the first ring is empty and the second ring is not empty then using the second tail pointer to read a second value from the second ring, wherein the reading of (g) is performed by a stage of the pipeline other than the first stage, wherein no stage of the pipeline has an instruction counter, and wherein no stage of the pipeline fetches, decodes and executes instructions.

8. The method of claim 7 , wherein the first stage of the pipeline uses the first head pointer and the first tail pointer to determine if the first ring is empty, and wherein the first stage of the pipeline uses the second head pointer and the second tail pointer to determine if the second ring is empty.

9. The method of claim 7 , wherein the first stage of the pipeline includes a first and a second count of entries value, wherein the first stage of the pipeline compares the first count of entries value with a first preset value to determine if the first ring is empty, and wherein the first stage of the pipeline compares the second count of entries value with a second preset value to determine if the second ring is empty.

10. The method of claim 7 , wherein the pipeline is clocked by a clock signal, and wherein the first stage processes a different command each cycle of the clock signal.

11. The method of claim 7 , wherein if a value is read from either the first or the second rings as a result of carrying out the get from one of a set of rings command then the value read is output from the transactional memory and onto the bus.

12. The method of claim 7 , further comprising: (h) if both the first and second rings are empty then not performing any read of either ring but rather outputting an error message from the transactional memory onto the bus, wherein the outputting of the error message is performed by a stage of the pipeline other than the first stage.

13. The method of claim 7 , wherein the get from one of a set of rings command identifies a set of rings, wherein the rings of the set have an ordered priority, and wherein execution of the get from one of a set of rings command causes the transactional memory to read a value from the highest priority one of the rings that is not empty.

14. The method of claim 7 , wherein there may be more than two rings in the set.

15. The method of claim 7 , wherein the first stage of the pipeline also maintains a first base address value for the first ring, and also maintains a second base address value for the second ring.

16. A transactional memory, comprising: a memory unit that stores a first ring of buffers and a second ring of buffers, wherein the first ring of buffers includes a first tail buffer and a first head buffer, and wherein the second ring of buffers includes a second tail buffer and a second head buffer; and means for: 1) receiving a get from one of a set of rings command onto the transactional memory from a bus, 2) using a first head pointer and a first tail pointer to determine if the first ring is empty, 3) using a second head pointer and a second tail pointer to determine if the second ring if empty, 4) if the first ring is not empty then reading a first value from the first ring, whereas if the first ring is empty and the second ring is not empty then reading a second value from the second ring, whereas if both the first and second rings are empty then not reading any value out of either the first ring or the second ring, 5) maintaining the first head pointer so that the first head pointer points to the first head buffer of the first ring, maintaining the first tail pointer so that the first tail pointer points to the first tail buffer of the first ring, maintaining the second head pointer so that the second head pointer points to the second head buffer of the second ring, maintaining the second tail pointer so that the second tail pointer points to the second tail buffer of the second ring, wherein the means does not have an instruction counter.

17. The transactional memory of claim 16 , wherein the means is also for: 6) if both the first and second rings are empty then not performing any read of either ring but rather outputting an error message onto the bus.

18. The transactional memory of claim 16 , wherein the means is a pipeline, wherein the pipeline includes a ring operation stage, a read stage and a write stage, and wherein the ring operation stage can be performing a task of a first command at the same time that the read stage is performing a task of a second command at the same time that the write stage is performing a task of a third command.

19. The transactional memory of claim 18 , wherein the pipeline is clocked by a clock signal, and wherein the ring operation stage processes a different command each cycle of the clock signal.

20. The transactional memory of claim 16 , wherein the get from one of a set of rings command identifies a set of rings, wherein the rings of the set have an ordered priority, and wherein execution of the get from one of a set of rings command causes the transactional memory to read a value from the highest priority one of the rings that is not empty.

21. The transactional memory of claim 16 , wherein the means is a pipeline, wherein the pipeline includes a ring operation stage, a read stage and a write stage, and wherein the ring operation stage stores for the first ring: the first head pointer, the first tail pointer, and a first base address value, and wherein the ring operation stage stores for the second ring: the second head pointer, the second tail pointer, and a second base address value.

22. The transactional memory of claim 16 , wherein the means is also for: 6) receiving a put into ring command.

23. The transactional memory of claim 16 , wherein the get from one of a set of rings command identifies a set of rings, wherein the rings of the set have an ordered priority, and wherein execution of the get from one of a set of rings command causes the transactional memory to read a value from the highest priority one of the rings that is not empty.

24. The transactional memory of claim 16 , wherein there may be more than two rings in the set.