Electronic Circuit for Fitting a Virtual Address Range to a Physical Memory Containing Faulty Address

1. An integrated circuit structure, comprising: a memory under repair having variable size blocks of failed memory addresses; a Ternary Content Addressable Memory (TCAM) comprising cells storing data values comprising ranges of addresses, said ranges of addresses corresponding to virtual addresses that, in combination with an offset value, point away from failed memory addresses in said memory under repair; a reduction circuit operatively connected to said TCAM, said reduction circuit producing a single output for each programmed range of said ranges of said addresses, based on a virtual address input to said TCAM; a priority encoder operatively connected to said reduction circuit, said priority encoder selecting a first programmed range from said reduction circuit; a random-access memory (RAM) operatively connected to said priority encoder, said RAM comprising cells storing data values comprising said offset value for each range of said ranges of said addresses; and an adder having two inputs, a first input being operatively connected to said RAM and a second input being operatively connected to a virtual address line, responsive to a virtual address being an address in one of said ranges of said addresses, said priority encoder passing said first programmed range containing said virtual address to said RAM, said RAM passing an offset value to said adder, said offset value corresponding to said first programmed range from said priority encoder, and said adder calculating a physical memory address directing said virtual address to a functional memory location in said memory under repair.

2. The integrated circuit structure according to claim 1 , said memory under repair comprising one of: SRAM; DRAM; eDRAM; MRAM; PCM; and Flash.

3. The integrated circuit structure according to claim 1 , contents for said TCAM and said RAM being generated separate from said integrated circuit structure.

4. The integrated circuit structure according to claim 3 , said contents of said TCAM and said RAM being programmed in at power-up of said integrated circuit structure.

5. The integrated circuit structure according to claim 1 , said ranges of said addresses being arranged in said TCAM in increasing order.

6. The integrated circuit structure according to claim 1 , said reduction circuit comprising an OR-reduction circuit.

7. The integrated circuit structure according to claim 1 , said priority encoder testing each programmed range of said ranges of said addresses and passing said first programmed range for which a next smaller range is greater-than-or-equal.

8. A computer-implemented method, comprising: configuring a Ternary Content Addressable Memory (TCAM) with data values comprising ranges of addresses in a memory under repair having variable size blocks of failed memory addresses, using a computerized device, said ranges of addresses corresponding to virtual addresses that, in combination with an offset value, point away from failed memory addresses in said memory under repair; receiving a virtual address, using said computerized device; applying at least a portion of said virtual address to said TCAM, using said computerized device; identifying a match in said TCAM indicating said virtual address being in said ranges of addresses, using said computerized device; producing a single output for each programmed range of said ranges of said addresses, based on said virtual address, using said computerized device; selecting a first programmed range from said ranges of addresses, using said computerized device; passing said first programmed range to a random-access memory (RAM), using said computerized device; outputting a corresponding offset value from said RAM as a first input to an adder, using said computerized device, said corresponding offset value corresponding to said first programmed range; applying said virtual address as a second input to said adder, using said computerized device; and mapping said virtual address to a physical address for a functional memory address in said memory under repair, using said computerized device.

9. The computer-implemented method according to claim 8 , said memory under repair comprising one of: SRAM; DRAM; eDRAM; MRAM; PCM; and Flash.

10. The computer-implemented method according to claim 8 , said configuring said TCAM with data values comprising ranges of addresses comprising generating contents for said TCAM and said RAM identifying unused functional memory locations in said memory under repair.

11. The computer-implemented method according to claim 8 , said ranges of said addresses being arranged in said TCAM in increasing order.

12. The computer-implemented method according to claim 8 , each entry in said RAM comprising an offset value for each range of said ranges of addresses in said memory under repair.

13. The computer-implemented method according to claim 12 , said mapping comprising said adder adding said offset value to said virtual address.

14. The computer-implemented method according to claim 13 , further comprising: programming contents of said TCAM and said RAM at power-up; and arranging said contents of said TCAM in increasing order.

15. A system, comprising: a memory under repair having variable size blocks of failed memory addresses; a Ternary Content Addressable Memory (TCAM) comprising cells storing data values comprising ranges of addresses; a reduction circuit operatively connected to said TCAM; a priority encoder operatively connected to said reduction circuit; a random-access memory (RAM) operatively connected to said priority encoder, said RAM comprising cells storing data values comprising an offset value for each range of said ranges of addresses; and a processor that identifies ranges of addresses in said memory under repair, said ranges of addresses corresponding to virtual addresses that, in combination with an offset value, point away from failed memory addresses in said memory under repair, identifies unused functional memory locations in said memory under repair, receives a virtual address and produces a single output for each programmed range of said ranges of addresses, using said reduction circuit, selects a first programmed range from said reduction circuit, using said priority encoder, based on said virtual address, calculates a physical memory address in an unused functional memory location in said memory under repair for said virtual address based on said virtual address and a corresponding offset value, said corresponding offset value corresponding to said first programmed range, and directs said virtual address to said physical memory address in said unused functional memory location.

16. The system according to claim 15 , said memory under repair comprising one of: SRAM; DRAM; eDRAM; MRAM; PCM; and Flash.

17. The system according to claim 15 , contents of said TCAM and said RAM being programmed in at power-up of said system.

18. The system according to claim 15 , said ranges of addresses being arranged in said TCAM in increasing order.

19. The system according to claim 15 , said reduction circuit comprising an OR-reduction circuit.

20. The system according to claim 15 , said priority encoder testing each programmed range of said ranges of addresses and passing said first programmed range for which a next smaller range is greater-than-or-equal.