Dual Regulator Systems

1. A method performed by a power state controller of a microcontroller system, the method comprising: enabling a main voltage regulator, the main voltage regulator being coupled to a core power supply of the microcontroller system and a core logic of the microcontroller system, the main voltage regulator providing a regulated voltage to the core logic; determining to enter a power saving mode; enabling a low power voltage regulator by using an enable signal from the power state controller, the low power voltage regulator having a low static current consumption less than a main static current consumption of the main voltage regulator, the low power voltage regulator being coupled to the core power supply and the core logic; receiving, by circuitry of the power state controller, a ready signal from the low power voltage regulator and the enable signal from the power state controller; and disabling the main voltage regulator by an output signal from the circuitry that is based on the enable signal from the power state controller and the ready signal from the low power voltage regulator so that the low power voltage regulator provides the regulated voltage to the core logic, wherein the circuitry comprises a first logic gate and a second logic gate, wherein disabling the main voltage regulator comprises providing the enable signal to a first input of the first logic gate and the ready signal to a second input of the first logic gate and providing the output signal from a first output of the first logic gate to the main voltage regulator, and wherein enabling a low power voltage regulator comprises providing the enable signal to a third input of the second logic gate and a second ready signal from the main voltage regulator to a fourth input of the second logic gate and providing a second output signal from a second output of the second logic gate to the low power voltage regulator.

2. The method of claim 1 , wherein both the low power voltage regulator and the main voltage regulator are providing the regulated voltage to the core logic during a time between enabling the low power voltage regulator and determining that the low power voltage regulator is ready.

3. The method of claim 1 , wherein the low power voltage regulator has a low current capability less than a main current capability of the main voltage regulator.

4. The method of claim 1 , wherein the low power voltage regulator is configured to start up after receiving the enable signal from the power state controller and to provide the ready signal when the low power voltage regulator has completed starting up.

5. The method of claim 1 , wherein enabling the low power voltage regulator comprises providing the enable signal without waiting for a clock signal to rise or fall.

6. A method performed by a power state controller of a microcontroller system, the method comprising: determining to exit a power saving mode, wherein, during the power saving mode, a low power voltage regulator is providing a regulated voltage to a core logic of the microcontroller system, the low power voltage regulator being coupled to a core power supply of the microcontroller system and the core logic; enabling a main voltage regulator by using an enable signal from the power state controller, the main voltage regulator being coupled to the core power supply and the core logic, the main voltage regulator having a main static current consumption higher than a low static current consumption of the low power voltage regulator; receiving, by circuitry of the power state controller, a ready signal from the main voltage regulator and the enable signal from the power state controller; and disabling the low power voltage regulator by an output signal from the circuitry that is based on the enable signal from the power state controller and the ready signal from the main voltage regulator so that the main voltage regulator provides the regulated voltage to the core logic, wherein the circuitry comprises a first logic gate and a second logic gate, wherein disabling the low power voltage regulator comprises providing the enable signal to a first input of the first logic gate and the ready signal to a second input of the first logic gate and providing the output signal from a first output of the first logic gate to the low power voltage regulator; and wherein enabling a main voltage regulator comprises providing the enable signal to a third input of the second logic gate and a second ready signal from the low power voltage regulator to a fourth input of the second logic gate and providing a second output signal from a second output of the second logic gate to the main voltage regulator.

7. The method of claim 6 , further comprising providing an additional voltage to the core logic from an energy storage unit during a time between enabling the main voltage regulator and determining that the main voltage regulator is ready.

8. The method of claim 6 , wherein the low power voltage regulator has a low current capability less than a main current capability of the main voltage regulator.

9. The method of claim 6 , wherein enabling the main voltage regulator comprises providing the enable signal without waiting for a clock signal to rise or fall.

10. A system comprising: a core logic; a main voltage regulator coupled to the core logic; a low power voltage regulator coupled to the core logic, the low power voltage regulator configured to have a low static current consumption less than a main static current consumption of the main voltage regulator; and a power state controller comprising circuitry coupled to the main voltage regulator and the low power voltage regulator, the circuitry configured to receive a ready signal from the low power voltage regulator, wherein the power state controller is configured to: enabling the low power voltage regulator using an enable signal from the power state controller, and disable the main voltage regulator by an output signal from the circuitry that is based on the enable signal from the power state controller and the ready signal from the low power voltage regulator, wherein the circuitry comprises: a first logic gate including a first input coupled to the power state controller, a second input coupled to a ready output of the low power voltage regulator, and a first output coupled to an enable input of the main voltage regulator; and a second logic gate including a third input coupled to the power state controller, a fourth input coupled to a ready output of the main voltage regulator, and a second output coupled to an enable input of the low power voltage regulator.

11. The system of claim 10 , wherein the low power voltage regulator has a low current capability less than a main current capability of the main voltage regulator.

12. The system of claim 10 , further comprising an energy storage unit configured to provide an additional voltage to the core logic during a time between enabling the main voltage regulator and determining that the main voltage regulator is ready.

13. The system of claim 12 , wherein the energy storage unit is a decoupling capacitor.

14. The system of claim 10 , wherein the main voltage regulator and the low voltage regulator are configured to concurrently supply a regulated voltage to the core logic during a time between enabling the main voltage regulator and determining that the main voltage regulator is ready.

15. The system of claim 10 , wherein the main voltage regulator and the low power voltage regulator are configured to concurrently supply a regulated voltage to the core logic during a time between enabling the low power voltage regulator and determining that the low power voltage regulator is ready.

16. The system of claim 10 , wherein the power state controller is configured to initiate a power saving mode, and the circuitry is further configured to disable the main voltage regulator based at least in part on the initiation of the power saving mode.

17. The system of claim 10 , wherein the power state controller is configured to: enable the low power voltage regulator by using the enable signal from the power state controller and a second ready signal from the main voltage regulator during the power saving mode and disable the main voltage regulator by using the enable signal from the power state controller and the ready signal from the low power voltage regulator after determining that the low power voltage regulator is ready; and on exiting the power saving mode, enable the main voltage regulator by using a second enable signal from the power state controller and the ready signal from the low power voltage regulator and disable the low power voltage regulator by using the second enable signal from the power state controller and the second ready signal from the main voltage regulator after determining that the main voltage regulator is ready.

18. The system of claim 17 , wherein the power state controller is configured to determine that the low power voltage regulator is ready by determining that the circuitry receives the ready signal from the low power voltage regulator and determine that the main voltage regulator is ready by determining that the circuitry receives the second ready signal from the main voltage regulator.

19. The system of claim 18 , wherein the main voltage regulator comprises a ready output and an enable input, wherein the main voltage regulator is configured to start up after receiving the second enable signal on the enable input from the power state controller, and wherein the main voltage regulator is configured to provide the second ready signal on the ready output when the main voltage regulator has completed starting up.

20. The system of claim 10 , wherein the low power voltage regulator is configured to start up after receiving the enable signal on the enable input from the power state controller, and wherein the low power voltage regulator is configured to provide the ready signal on the ready output when the low power voltage regulator has completed starting up.

21. The system of claim 10 , wherein the power state controller provides the enable signal to the first input of the first logic gate and the second input of the second logic gate, and wherein the power state controller enables the low power voltage regulator when the power state controller drives the enable signal high, and the power state controller enables the main voltage regulator when the power state controller drives the enable signal low.

22. The system of claim 21 , wherein the first logic gate is an NAND logic gate and the second logic gate is an OR gate, and wherein the third input of the OR gate is a non-inverted input and the fourth input of the OR gate is an inverted input.