Phase Interpolator Circuit, Clock Data Recovery Circuit Including the Same, and Phase Interpolation Method

1. A phase interpolator circuit comprising: an interpolator suitable for generating synthesized clocks through synthesizing two multi-phase clocks that are selected from first to N-th multi-phase clocks, wherein N is an integer greater than or equal to 3; and an interpolation code generator suitable for generating an interpolation code for controlling the interpolator in response to a shift-up request, a shift-down request, a multi-shift-up request, and a multi-shift-down request, wherein the interpolation code generator generates the interpolation code so that a (K+1)-th multi-phase clock is output as the synthesized clock when a phase of the synthesized clock should be changed from a phase between K-th and (K+1)-th multi-phase clocks to a phase between (K+1)-th and (K+2)-th multi-phase clocks in response to the multi-shift-up request, wherein K is an integer greater than or equal to 1 and less than or equal to N, in the case of K-th being N-th, (K+1)-th is first, and in the case of K-th being first, (K−1)-th is N-th.

2. The phase interpolator circuit of claim 1 , wherein the interpolation code generator further generates the interpolation code so that the K-th multi-phase clock is output as the synthesized clock when the phase of the synthesized clock should be changed from the phase between the K-th and (K+1)-th multi-phase clocks to a phase between (K−1)-th and K-th multi-phase clocks in response to the multi-shift-down request.

3. The phase interpolator circuit of claim 2 , wherein the interpolator comprises: a clock selector suitable for selecting the two multi-phase clocks from the first to N-th multi-phase clocks in response to first bits of the interpolation code; and a clock mixer suitable for generating the synthesized clocks through synthesizing the two multi-phase clocks that are selected by the clock selector at a synthesis ratio that is determined by second bits of the interpolation code.

4. The phase interpolator circuit of claim 3 , wherein the interpolation code generator comprises: a preliminary interpolation code generator suitable for increasing by one step a preliminary interpolation code in response to the shift-up request, for increasing by two steps the preliminary interpolation code in response to the multi-shift-up request, for decreasing by one step the preliminary interpolation code in response to the shift-down request, and for decreasing by two steps the preliminary interpolation code in response to the multi-shift-down request; and a code corrector which: decrease by one step the preliminary interpolation code and output the decreased preliminary interpolation code as the interpolation code when the phase of the synthesized clock changes from the phase between the K-th and (K+1)-th multi-phase clocks to the phase between the (K+1)-th and (K+2)-th multi-phase clocks in response to the multi-shift-up request, increase by one step the preliminary interpolation code and output the increased preliminary interpolation code as the interpolation code when the phase of the synthesized clock should be changed from the phase between the K-th and (K+1)-th multi-phase clocks to the phase between (K−1)-th and K-th multi-phase clocks in response to the multi-shift-down request, and output the preliminary interpolation code as the interpolation code otherwise.

5. A phase interpolation method comprising: selecting two multi-phase clocks from first to N-th multi-phase clocks in response to first bits of an interpolation code, wherein N is an integer greater than or equal to 3; generating synthesized clocks through synthesizing the two multi-phase clocks at a synthesis ratio that is determined by second bits of the interpolation code; increasing by one step a preliminary interpolation code in response to a shift-up request; generating the interpolation code so that the interpolation code has the same value as the preliminary interpolation code when the preliminary interpolation code is increased by one step; increasing by two steps the preliminary interpolation code in response to a multi-shift-up request; and generating the interpolation code by decreasing by one step the preliminary interpolation code when the preliminary interpolation code is increased by two steps and a phase of the synthesized clock is changed from a phase between K-th and (K+1)-th multi-phase clocks to a phase between (K+1)-th and (K+2)-th multi-phase clocks, wherein K is an integer that is greater than or equal to 1 and less than or equal to N, in the case of K-th being N-th, (K+1)-th is first, and in the case of K-th being first, (K−1)-th is N-th, and generating the interpolation code so that the interpolation code has the same value as the preliminary interpolation code otherwise.

6. The phase interpolation method of claim 5 , further comprising: decreasing by one step the preliminary interpolation code in response to a shift-down request; generating the interpolation code in the same manner as the preliminary interpolation code when the preliminary interpolation code is decreased by one step; decreasing by two steps the preliminary interpolation code in response to a multi-shift-down request; and generating the interpolation code by increasing by one step the preliminary interpolation code when the preliminary interpolation code is decreased by two steps, and the phase of the synthesized clock is changed from the phase between the K-th and (K+1)-th multi-phase clocks to a phase between (K−1)-th and K-th multi-phase clocks, and generating the interpolation code in the same manner as the preliminary interpolation code otherwise.

7. A clock data recovery circuit comprising: a phase comparator suitable for comparing phases of received data and a recovered clock; a request generator suitable for generating a shift-up request, a multi-shift-up request, a shift-down request, and a multi-shift-down request in response to the comparison result of the phase comparator; an interpolator suitable for generating synthesized clocks through synthesizing two multi-phase clocks that are selected from first to N-th multi-phase clocks, wherein N is an integer greater than or equal to 3; and an interpolation code generator suitable for generating an interpolation code for controlling the interpolator in response to the shift-up request, the shift-down request, the multi-shift-up request, and the multi-shift-down request, wherein the interpolation code generator generates the interpolation code so that the (K+1)-th multi-phase clock is output as the synthesized clock when a phase of the synthesized clock should be changed from a phase between K-th and (K+1)-th multi-phase clocks to a phase between (K+1)-th and (K+2)-th multi-phase clocks in response to the multi-shift-up request, wherein K is an integer greater than or equal to 1 and less than or equal to N, in the case of K-th being N-th, (K+1)-th is first, and in the case of K-th being first, (K−1)-th is N-th.

8. The clock data recovery circuit of claim 7 , wherein the interpolation code generator further generates the interpolation code so that the K-th multi-phase clock is output as the synthesized clock when the phase of the synthesized clock should be changed from the phase between the K-th and (K+1)-th multi-phase clocks to a phase between (K−1)-th and K-th multi-phase clocks in response to the multi-shift-down request.

9. The clock data recovery circuit of claim 8 , wherein the interpolator comprises: a clock selector suitable for selecting the two multi-phase clocks from the first to N-th multi-phase clocks in response to first bits of the interpolation code; and a clock mixer suitable for generating the synthesized clocks through synthesizing the two multi-phase clocks that are selected by the clock selector at a synthesis ratio that is determined by second bits of the interpolation code.

10. The clock data recovery circuit of claim 9 , wherein the interpolation code generator comprises: a preliminary interpolation code generator suitable for increasing by one step a preliminary interpolation code in response to the shift-up request, for increasing by two steps the preliminary interpolation code in response to the multi-shift-up request, for decreasing by one step the preliminary interpolation code in response to the shift-down request, and for decreasing by two steps the preliminary interpolation code in response to the multi-shift-down request; and a code corrector which: decreases by one step the preliminary interpolation code and outputs the decreased preliminary interpolation code as the interpolation code when the phase of the synthesized clock should be changed from the phase between the K-th and (K+1)-th multi-phase clocks to the phase between the (K+1)-th and (K+2)-th multi-phase clocks in response to the multi-shift-up request, increases by one step the preliminary interpolation code and outputs the increased preliminary interpolation code as the interpolation code when the phase of the synthesized clock should be changed from the phase between the K-th and (K+1)-th multi-phase clocks to the phase between (K−1)-th and K-th multi-phase clocks in response to the multi-shift-down request, and outputs the preliminary interpolation code as the interpolation code otherwise.

11. The clock data recovery circuit of claim 9 , further comprising a phase locked loop suitable for generating the first to N-th multi-phase clocks.

12. A phase interpolator circuit comprising: an interpolator suitable for generating a synthesized clock by synthesizing two selected from plural multi-phase clocks according to an interpolation code, wherein the selected multi-phase clocks form a phase region; and an interpolation code generator suitable for generating the interpolation code in response to a shift request, wherein the interpolation code generator adjusts the interpolation code in order to control the interpolator to generate the synthesized clock having a boundary phase between first and second phase regions when the shift request represents the synthesized clock shifting from one to the other between the first and second phase regions, wherein the shift request is either a multi-shift-up request or a multi-shift-down request, wherein the multi-shift-up request represents shifting up the synthesized clock by two or more phase steps from a current phase, and wherein the multi-shift-down request represents shifting down the synthesized clock by two or more phase steps from the current phase.

13. The phase interpolator circuit of claim 12 , wherein the interpolation code generator comprises: a preliminary interpolation code generator suitable for generating the interpolation code in response to the shift request; and a code corrector which adjusts the interpolation code to represent shifting up or down the synthesized clock by a single phase step from a current phase when the shift request represent the synthesized clock shifting from one to the other between the first and second phase regions.

14. The phase interpolator circuit of claim 12 , wherein the interpolator comprises: a clock selector suitable for selecting the two multi-phase clocks according to first bits of the interpolation code; and a clock mixer suitable for generating the synthesized clocks by synthesizing the two multi-phase clocks at a synthesis ratio defined by second bits of the interpolation code.

15. A clock data recovery circuit comprising: a phase comparator suitable for comparing phases of received data and a recovered clock; a request generator suitable for generating a shift request according to the comparison result; an interpolator suitable for generating a synthesized clock by synthesizing two selected from plural multi-phase clocks according to an interpolation code, wherein the selected multi-phase clocks form a phase region; and an interpolation code generator suitable for generating the interpolation code in response to the shift request, wherein the interpolation code generator adjusts the interpolation code in order to control the interpolator to generate the synthesized clock having a boundary phase between first and second phase regions when the shift request represent the synthesized clock shifting from one to the other between the first and second phase regions, wherein the shift request is either a multi-shift-up request or a multi-shift-down request, wherein the multi-shift-up request represents shifting up the synthesized clock by two or more phase steps from a current phase, and wherein the multi-shift-down request represents shifting down the synthesized clock by two or more phase steps from the current phase.

16. The clock data recovery circuit of claim 15 , wherein the interpolation code generator comprises: a preliminary interpolation code generator suitable for generating the interpolation code in response to the shift request; and a code corrector which adjusts the interpolation code to represent shifting up or down the synthesized clock by a single phase step from a current phase when the shift request represents the synthesized clock shifting from one to the other between the first and second phase regions.

17. The clock data recovery circuit of claim 15 , wherein the interpolator comprises: a clock selector suitable for selecting the two multi-phase clocks according to first bits of the interpolation code; and a clock mixer suitable for generating the synthesized clocks by synthesizing the two multi-phase clocks at a synthesis ratio defined by second bits of the interpolation code.