Data Storing Method and Memory Controller and Memory Storage Device Using the Same

1. A data storing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erase units, each of the physical erase units has a plurality of physical program units, and the physical erase units are grouped into at least a system area, the data storing method comprising: writing system data into a first physical erase unit in the system area; determining whether the first physical erase unit contains a dancing bit; and when the first physical erase unit contains the dancing bit, selecting a second physical erase unit among the physical erase units, and writing the system data into the second physical erase unit.

2. The data storing method according to claim 1 further comprising: moving valid data in the first physical erase unit into the second physical erase unit.

3. The data storing method according to claim 2 further comprising: after moving the valid data in the first physical erase unit into the second physical erase unit, executing an erasing operation on the first physical erase unit.

4. The data storing method according to claim 1 , wherein the step of determining whether the first physical erase unit contains the dancing bit comprises: determining whether the number of error bits in data stored in a first physical program unit among the physical program units of the first physical erase unit is greater than an error bit number threshold and not greater than a maximum correctable error bit number, wherein the system data is written into the first physical program unit; and when the number of error bits in the data stored in the first physical program unit is greater than the error bit number threshold and not greater than the maximum correctable error bit number, determining that the first physical erase unit contains the dancing bit.

5. A memory controller for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erase units, each of the physical erase units has a plurality of physical program units, the memory controller comprising: a host interface configured to couple to a host system; a memory interface configured to couple to the rewritable non-volatile memory module; and a memory management circuit coupled to the host interface and the memory interface, wherein the memory management circuit groups the physical erase units into at least a system area, wherein the memory management circuit writes system data into a first physical erase unit in the system area, and determines whether the first physical erase unit contains a dancing bit, wherein if the first physical erase unit contains the dancing bit, the memory management circuit selects a second physical erase unit among the physical erase units and writes the system data into the second physical erase unit.

6. The memory controller according to claim 5 , wherein the memory management circuit moves valid data in the first physical erase unit into the second physical erase unit.

7. The memory controller according to claim 6 , wherein after moving the valid data in the first physical erase unit into the second physical erase unit, the memory management circuit executes an erasing operation on the first physical erase unit.

8. The memory controller according to claim 5 , wherein in the operation of determining whether the first physical erase unit contains the dancing bit, the memory management circuit determines whether the number of error bits in data stored in a first physical program unit among the physical program units of the first physical erase unit is greater than an error bit number threshold and not greater than a maximum correctable error bit number, wherein the system data is written into the first physical program unit, wherein if the number of error bits in the data stored in the first physical program unit is greater than the error bit number threshold and not greater than the maximum correctable error bit number, the memory management circuit determines that the first physical erase unit contains the dancing bit.

9. A memory storage device, comprising: a connector configured to couple to a host system; a rewritable non-volatile memory module having a plurality of physical erase units, wherein each of the physical erase units has a plurality of physical program units; and a memory controller coupled to the connector and the rewritable non-volatile memory module, wherein the memory controller groups the physical erase units into at least a system area, wherein the memory controller writes system data into a first physical erase unit in the system area, and determines whether the first physical erase unit contains a dancing bit, wherein if the first physical erase unit contains the dancing bit, the memory controller selects a second physical erase unit among the physical erase units and writes the system data into the second physical erase unit.

10. The memory storage device according to claim 9 , wherein the memory controller moves valid data in the first physical erase unit into the second physical erase unit.

11. The memory storage device according to claim 10 , wherein after moving the valid data in the first physical erase unit into the second physical erase unit, the memory controller executes an erasing operation on the first physical erase unit.

12. The memory storage device according to claim 9 , wherein in the operation of determining whether the first physical erase unit contains the dancing bit, the memory controller determines whether the number of error bits in data stored in a first physical program unit among the physical program units of the first physical erase unit is greater than an error bit number threshold and not greater than a maximum correctable error bit number, wherein the system data is written into the first physical program unit, wherein if the number of error bits in the data stored in the first physical program unit is greater than the error bit number threshold and not greater than the maximum correctable error bit number, the memory management circuit determines that the first physical erase unit contains the dancing bit.