Method And Apparatus For Conditional Storing Of Data Using A Compare-And-Swap Based Approach

1. A method of conditionally storing data, the method comprising: initiating, by a core processor, an atomic sequence by executing a load operation designed to initiate the atomic sequence, executing the load operation designed to initiate the atomic sequence includes loading content of a memory location and maintaining an address indication of the memory location and a copy of the corresponding content loaded; and performing a conditional storing operation, the conditional storing operation includes a compare-and-swap operation, the compare-and-swap operation executed by a controller associated with a cache memory based on the address indication of the memory location and the copy of the corresponding content maintained; wherein the loaded content is loaded in a first cache memory and the cache memory with which the controller is associated is a second memory cache, the method further comprising providing, by the core processor, the address indication of the memory location and the copy of the corresponding content to the second cache memory.

2. The method as recited in claim 1 , wherein performing the conditional storing operation includes performing the conditional storing operation upon determining that one or more constraints are satisfied.

3. The method as recited in claim 2 , wherein the one or more constraints include the atomic sequence not being interrupted at the core processor.

4. The method as recited in claim 2 , wherein the one or more constraints include the conditional store operation not being failed by the core processor.

5. The method as recited in claim 4 , wherein the conditional storing operation is failed by the core processor if the memory location loaded is invalidated in the first memory cache prior to performing the conditional store operation, and based on a value of a counter, the counter being indicative of a number of times the conditional store operation is failed by the core processor due to an invalidation instruction from the second cache memory.

6. The method as recited in claim 5 , wherein the counter is reset upon resetting the core processor or if the conditional store operation is failed by the core processor due to any reason other than an invalidation instruction from the second cache memory.

7. The method as recited in claim 5 , wherein the counter is incremented each time the conditional storing operation is failed by the core processor due to an invalidation instruction from the second cache memory.

8. The method as recited in claim 2 , wherein the one or more constraints include the conditional storing operation not being failed at the second cache memory.

9. The method as recited in claim 8 , wherein the conditional storing operation is failed by the controller if the memory location loaded, upon being passed to the second cache memory, is invalidated in the second cache memory prior to performing the conditional storing operation.

10. The method as recited in claim 1 , wherein the compare-and-swap operation includes: comparing, by the controller, the copy of the content maintained with content corresponding to the memory location; performing, by the controller, the conditional store operation if a match is found between the copy of the content maintained and the content corresponding to the memory location; and failing, by the controller, the conditional storing operation if no match is found between the copy of the content maintained and the content corresponding to the memory location.

11. A multi-core processor device comprising: multiple core processors, each having a corresponding first cache memory; and a second cache memory including a corresponding controller, the second cache memory being accessible by the multiple core processors, a core processor of the multiple core processors being configured to: initiate the atomic sequence by executing a load operation designed to initiate an atomic sequence, executing the load operation designed to initiate the atomic sequence includes loading content of a memory location and maintaining an address indication of the memory location and a copy of the corresponding content loaded; and the controller being configured to perform a conditional storing operation, the conditional storing operation includes a compare-and-swap operation, the compare-and-swap operation being executed by the controller based on the address indication of the memory location and the copy of the corresponding content maintained; wherein the loaded content is loaded in the first cache memory of the core processor, the core processor is further configured to provide the address indication of the memory location and the copy of the corresponding content to the second cache memory.

12. The multi-core processor device as recited in claim 11 , wherein the conditional storing operation is performed by the controller upon determining that one or more constraints are satisfied.

13. The multi-core processor device as recited in claim 12 , wherein the one or more constraints include the atomic sequence not being interrupted at the core processor.

14. The multi-core processor device as recited in claim 12 , wherein the one or more constraints include the conditional storing operation not being failed by the core processor.

15. The multi-core processor device as recited in claim 14 , wherein the core processor is configured to fail the conditional storing operation if the content of the memory location loaded is invalidated in the first memory cache prior to performing the conditional storing operation and based on a value of a counter, the counter being indicative of a number of times the conditional storing operation is failed by the core processor due to an invalidation instruction from the controller.

16. The multi-core processor device as recited in claim 15 , wherein the core processor is further configured to reset the counter upon a reset of the core processor or if the conditional storing operation is failed by the core processor due to any reason other than an invalidation instruction from the controller.

17. The multi-core processor device as recited in claim 16 , wherein the core processor is further configured to increment the counter each time the conditional storing operation is failed by the core processor due to an invalidation instruction from the controller.

18. The multi-core processor device as recited in claim 12 , wherein the one or more constraints include the conditional storing operation not being failed at the second cache memory.

19. The multi-core processor device as recited in claim 12 , wherein the controller is configured to fail the conditional storing operation if the memory location loaded, upon being passed to the second memory cache, is invalidated in the second memory cache prior to performing the conditional store operation.

20. The multi-core processor device as recited in claim 11 , wherein in executing the compare-and-swap operation, the controller is configured to: compare the copy of the content maintained with content corresponding to the memory location; perform the conditional storing operation if a match is found between the copy of the content maintained and the content corresponding to the memory location; and fail the conditional storing operation if no match is found between the copy of the content maintained and the content corresponding to the memory location.

21. A processor device comprising: a core processor having a first cache memory, the core processor configured to: initiate an atomic sequence by executing a load operation designed to initiate the atomic sequence, executing the load operation designed to initiate the atomic sequence includes loading content of a memory location and maintaining an address indication of the memory location and a copy of the corresponding content loaded; and a controller configured to perform a conditional storing operation, the conditional storing operation includes a compare-and-swap operation, the compare-and-swap operation being executed by the controller based on the address indication of the memory location and the copy of the corresponding content maintained; wherein the loaded content is loaded in the first cache memory of the core processor, the core processor is further configured to provide the address indication of the memory location and the copy of the corresponding content to a second cache memory associated with the controller.