System and Method for Sending Arbitrary Packet Types Across a Data Connector

1. A computer-implemented method for transmitting packets from a first hardware unit to a second hardware unit across a data connector, the method comprising: receiving a first signal that corresponds to a first packet type; reading a first packet specification from a software register, wherein the first packet specification defines the first packet type; generating a packet according to the first packet type based on the first packet specification; and causing the packet to be transmitted from the first hardware unit to the second hardware unit across the data connector.

2. The computer-implemented method of claim 1 , wherein the first hardware unit writes the first packet specification to the software register.

3. The computer-implemented method of claim 1 , wherein the second hardware unit writes the first packet specification to the software register across the data connector.

4. The computer-implemented method of claim 1 , wherein the first packet specification includes a mapping from the first signal to the first packet type, and reading the first packet specification comprises identifying the first packet specification as including the mapping from the first signal to the first packet type.

5. The computer-implemented method of claim 1 , wherein the data connector comprises a peripheral component interconnect express (PCIe) or a universal serial bus (USB).

6. The computer-implemented method of claim 1 , wherein the first hardware unit comprises a graphics processing unit (GPU), and the second hardware unit comprises a central processing unit (CPU).

7. The computer-implemented method of claim 1 , wherein the first signal originates from a hardware element embedded within the first hardware unit or from a software application executing on the first hardware unit.

8. A subsystem included within a first hardware unit and configured to cause packets to be transmitted from the first hardware unit to a second hardware unit across a data connector by performing the steps of: receiving a first signal that corresponds to a first packet type; reading a first packet specification from a software register included within the first hardware unit, wherein the first packet specification defines the first packet type; generating a packet according to the first packet type based on the first packet specification; and causing the packet to be transmitted from the first hardware unit to the second hardware unit across the data connector.

9. The subsystem of claim 8 , wherein the first hardware unit writes the first packet specification to the software register.

10. The subsystem of claim 8 , wherein the second hardware unit writes the first packet specification to the software register across the data connector.

11. The subsystem of claim 8 , wherein the first packet specification includes a mapping from the first signal to the first packet type, and the step of reading the first packet specification comprises identifying the first packet specification as including the mapping from the first signal to the first packet type.

12. The subsystem of claim 8 , wherein the data connector comprises a peripheral component interconnect express (PCIe) or a universal serial bus (USB).

13. The subsystem of claim 8 , wherein the first hardware unit comprises a graphics processing unit (GPU), and the second hardware unit comprises a central processing unit (CPU).

14. The subsystem of claim 8 , wherein the first signal originates from a hardware element embedded within the first hardware unit or from a software application executing on the first hardware unit.

15. A computing device, including: a first hardware unit that includes a first subsystem; a second hardware unit; and a data connector that couples together the first hardware unit and the second hardware unit, wherein the first subsystem within the first hardware unit is configured to cause packets to be transmitted from the first hardware unit to the second hardware unit across the data connector by: receiving a first signal that corresponds to a first packet type, reading a first packet specification from a software register included within the first hardware unit, wherein the first packet specification defines the first packet type, generating a packet according to the first packet type based on the first packet specification, and causing the packet to be transmitted from the first hardware unit to the second hardware unit across the data connector.

16. The computing device of claim 15 , further including: a memory coupled to the first subsystem and storing program instructions that, when executed by the first subsystem, cause the first subsystem to: receive the first signal, read the first packet specification from the software register, generate the packet according to the first packet type, and cause the packet to be transmitted from the first hardware unit to the second hardware unit across the data connector.

17. The computing device of claim 15 , wherein the first hardware unit writes the first packet specification to the software register, or the second hardware unit writes the first packet specification to the software register across the data connector.

18. The computing device of claim 15 , wherein the first packet specification includes a mapping from the first signal to the first packet type, and reading the first packet specification comprises identifying the first packet specification as including the mapping from the first signal to the first packet type.

19. The computing device of claim 15 , wherein the first hardware unit comprises a graphics processing unit (GPU), the second hardware unit comprises a central processing unit (CPU), and the data connector comprises a peripheral component interconnect express (PCIe) or a universal serial bus (USB).

20. The computing device of claim 15 , wherein the first signal originates from a hardware element embedded within the first hardware unit or from a software application executing on the first hardware unit.