Power Rail for Preventing DC Electromigration

1. A method comprising: dividing a power rail in at least one design file of a semiconductor device into a plurality of metal segments, wherein each two of the neighboring metal segments are separated by a cut via that sinks electrons from the neighboring metal segments; determining sub-segment lengths of a plurality sub-segments in each of the metal segments, wherein each of the sub-segments starts from a starting via that injects electrons to the metal segments to a terminal of the metal segments; including each of the metal segments in the at least one design file with a current density limit depending on a maximum length of the sub-segment lengths; and fabricating, by using a fabrication system, the semiconductor device according to the at least one design file.

2. The method of claim 1 , wherein the current density limit is smaller when the maximum length is larger.

3. The method of claim 1 , further comprising a step of: electrically coupling the power rail to a power supply or a ground terminal.

4. The method of claim 1 , wherein the starting via is configured to inject the electrons to the power rail without sinking electrons.

5. The method of claim 1 , wherein the current density limit of the metal segments is smaller when the maximum length is larger.

6. The method of claim 1 , wherein the maximum length of the sub-segments is a longest possible distance of the migration of a plurality of metal atoms in the metal segments.

7. The method of claim 1 , wherein the metal segments are included in the at least one design file by using the maximum length as an effective length.

8. The method of claim 1 , wherein the power rail provides power to integrated circuit components of a device portion in the semiconductor device.

9. The method of claim 8 , further comprising including a plurality of signal lines that transmit data signals or clock signals between the integrated circuit components of the device portion in the at least one design file.

10. A non-transitory computer-readable medium containing therein instructions which, when executed by a processor of a computer system, cause the processor to execute a method comprising: dividing a power rail in at least one design file of a semiconductor device into a plurality of metal segments, wherein each two of the neighboring metal segments are separated by a cut via that sinks electrons from the neighboring metal segments; determining sub-segment lengths of a plurality sub-segments in each of the metal segments, wherein each of the sub-segments starts from a starting via that injects electrons to the metal segments to a terminal of the metal segments; and including each of the metal segments in the at least one design file with a current density limit depending on a maximum length of the sub-segment lengths; and fabricating, by using a fabrication system, the semiconductor device according to the at least one design file.

11. The non-transitory computer-readable medium of claim 10 , wherein the current density limit is smaller when the maximum length is larger.

12. The non-transitory computer-readable medium of claim 10 , wherein the method further comprises a step of: electrically coupling the power rail to a power supply or a ground terminal.

13. The non-transitory computer-readable medium of claim 10 , wherein the starting via is configured to inject the electrons to the power rail without sinking electrons.

14. The non-transitory computer-readable medium of claim 10 , wherein the current density limit of the metal segments is smaller when the maximum length is larger.

15. The non-transitory computer-readable medium of claim 10 , wherein the maximum length of the sub-segments is a longest possible distance of the migration of a plurality of metal atoms in the metal segments.

16. The non-transitory computer-readable medium of claim 10 , wherein the metal segments are included in the at least one design file by using the maximum length as an effective length.

17. The non-transitory computer-readable medium of claim 10 , wherein the power rail provides power to integrated circuit components of a device portion in the semiconductor device.

18. The non-transitory computer-readable medium of claim 17 , wherein the method further comprises including a plurality of signal lines that transmit data signals or clock signals between the integrated circuit components of the device portion in the at least one design file.

19. The non-transitory computer-readable medium of claim 10 , wherein the power rail is either coupled to a power supply or to a ground terminal.

20. A method comprising: dividing a power rail in at least one design file of a semiconductor device into a plurality of metal segments, wherein each two of the neighboring metal segments are separated by a cut via that sinks electrons from the neighboring metal segments, and the power rail is either coupled to a power supply or to a ground terminal; determining sub-segment lengths of a plurality sub-segments in each of the metal segments, wherein each of the sub-segments starts from a starting via that injects electrons to the metal segments to a terminal of the metal segments; including each of the metal segments in the at least one design file with a current density limit depending on a maximum length of the sub-segment lengths; and fabricating, by using a fabrication system, the semiconductor device according to the at least one design file.