9418471

Compact Depth Plane Representation for Sort Last Architectures

PublishedAugust 16, 2016
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
27 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method comprising: storing a depth plane representation for fully covered tiles; storing a depth plane representation for partially covered tiles at lower precision than for fully covered tiles stored at higher precision; and; using the depth plane representation to develop a depiction for display on a computer including a central processing unit.

2

2. The method of claim 1 including determining whether reconstructed depth values for partially covered tiles are the same as obtained with higher precision after rounding.

3

3. The method of claim 2 including using bits saved through the lower precision representation to store a compressed coverage mask.

4

4. The method of claim 3 including using bits saved through the lower precision representation to encode two planes overlapping a single tile.

5

5. The method of claim 3 , including storing signs, exponents and compressed per sample coverage mask.

6

6. The method of claim 5 , including encoding lower precision mantissa bits of a depth plane equation.

7

7. The method of claim 6 , including adapting the lower precision plane representation to make samples' depth values identical to the corresponding higher precision plane representation.

8

8. The method of claim 1 including using a graphics processor to store a depth plane representation.

9

9. One or more non-transitory computer readable media storing instructions executed by a processor to perform a sequence comprising: storing a depth plane representation for tiles that are fully covered by a primitive; and storing a depth plane representation for partially covered tiles at lower precision than for fully covered tiles stored at higher precision.

10

10. The media of claim 9 including determining whether reconstructed depth values for partially covered tiles are the same as values with the higher precision representation after rounding.

11

11. The media of claim 10 including using bits saved through the lower precision representation to store a compressed coverage mask.

12

12. The media of claim 11 including using bits saved through the lower precision representation to encode two planes overlapping a single tile.

13

13. The media of claim 11 , including storing signs, exponents and compressed per sample coverage mask.

14

14. The media of claim 13 , including encoding lower precision mantissa bits of a depth plane equation.

15

15. The media of claim 14 , including adapting the lower precision plane representation to make samples' depth values identical to the corresponding higher precision plane representation.

16

16. An apparatus comprising: a processor to store a depth plane representation for fully covered tiles and to store a depth plane representation for partially covered tiles at lower precision than for fully covered tiles stored at higher precision; and a memory coupled to said processor.

17

17. The apparatus of claim 16 , said processor to determine whether reconstructed depth values for partially covered tiles are the same as obtained with higher precision after rounding.

18

18. The apparatus of claim 17 , said processor to use bits saved through the lower precision representation to store a compressed coverage mask.

19

19. The apparatus of claim 18 , said processor to use bits saved through the lower precision representation to encode two planes overlapping a single tile.

20

20. The apparatus of claim 18 , said processor to store signs, exponents and compressed per sample coverage mask.

21

21. The apparatus of claim 20 , said processor to encode lower precision mantissa bits of a depth plane equation.

22

22. The apparatus of claim 21 , said processor to adapt the lower precision plane representation to make samples; depth values identical to the corresponding higher precision plane representation.

23

23. The apparatus of claim 16 wherein said processor is a graphics processor.

24

24. The apparatus of claim 23 including a rasterizer.

25

25. The apparatus of claim 16 including a display communicatively coupled to the processor.

26

26. The apparatus of claim 16 including a battery coupled to the processor.

27

27. The apparatus of claim 16 including firmware and a module to update said firmware.

Patent Metadata

Filing Date

Unknown

Publication Date

August 16, 2016

Inventors

Jon N. Hasselgren
Magnus Andersson

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Cite as: Patentable. “Compact Depth Plane Representation for Sort Last Architectures” (9418471). https://patentable.app/patents/9418471

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Compact Depth Plane Representation for Sort Last Architectures — Jon N. Hasselgren | Patentable