Multi-Level Memory with Direct Access

1. A method, comprising: designating a first amount of a non-volatile random access memory (NVRAM) for use as memory for a computing system; designating a second amount of the NVRAM for use as storage for the computing system; generating a memory remap table based on the first amount of the NVRAM designated for use as memory; generating a storage remap table based on the second amount of NVRAM designated for use as storage; and updating the memory and storage remap tables responsive to a first re-designation of a portion of the first amount of the NVRAM for use as storage or a second re-designation of a portion of the second amount of the NVRAM for use as memory.

2. The method of claim 1 , comprising: cycling through the entire first amount of NVRAM over a first amount of time to be re-designated from use as memory to use as storage, the cycling including re-designating each of a plurality of portions that make up the entire first amount of NVRAM at separate segments of a plurality of segments of time, the sum of the plurality of segments comprising the first amount of time.

3. The method of claim 1 , comprising: providing access to at least one physical location in the NVRAM for a software application running on the computer system through the memory remap table, the memory remap table arranged to translate at least a platform physical address to a physical NVRAM address.

4. The method of claim 1 , comprising the storage remap table arranged to translate at least a logical block address to a physical NVRAM address.

5. The method of claim 1 , comprising: generating a page status table having at least a bit associated with separate NVRAM physical pages of the NRAM in separate page status table entries, the separate page status table entries indicating whether a given NVRAM physical page corresponding to a given page status table entry is designated for use as memory or storage.

6. The method of claim 1 , comprising: determining, for separate NVRAM physical pages of a plurality of NVRAM physical pages, whether individual NVRAM physical pages are free to be written to, an individual NVRAM physical page is free to be written to when the individual NVRAM physical page is not holding valid data; and determining, for separately identified free NVRAM physical pages, whether the separately identified free NVRAM physical pages are clean, wherein a given free NVRAM physical page is clean when all stored bits in the given free NVRAM physical page are set to one.

7. The method of claim 6 , comprising: cleaning at least one separately identified free NVRAM physical page, wherein the at least one separately identified free NVRAM physical page to be cleaned includes at least one stored bit set to zero.

8. The method of claim 7 , comprising: monitoring an interface to access the NVRAM to determine whether the interface is substantially idle at any given time; receiving a write request from a requestor; providing at least one of the separately identified free NVRAM physical pages that has not been cleaned when the interface to access the NVRAM is substantially idle; and providing at least one of the separately identified free NVRAM physical pages that has been cleaned when the interface to access the NVRAM is not substantially idle.

9. The method of claim 1 , wherein the NVRAM comprises at least one of phase change memory, phase change memory and switch (PCMS), resistive memory (RRAM), ferroelectric memory, spin-transfer torque random access memory (STRAM), spin tunneling random access memory (SPRAM), magnetoresistive memory, magnetic memory, magnetic random access memory (MRAM) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory.

10. The method of claim 1 , comprising: designating the first amount of the NVRAM for use as memory includes arranging the first amount of the NVRAM to function as at least a portion of system memory for the computing system; and designating the second amount of the NVRAM for use as storage includes arranging the first amount of the NVRAM to function as mass storage for the computing system.

11. A device, comprising: a hardware control logic to: designate a first amount of a non-volatile random access memory (NVRAM) for use as memory for a computing system; designate a second amount of the NVRAM for use as storage for the computing system; generate a memory remap table based on the first amount of the NVRAIVI designated for use as memory; generate a storage remap table based on the second amount of the NVRAM designated for use as storage; and update the memory and storage remap tables responsive to a first re-designation of a portion of the first amount of the NVRAIVI for use as storage or a second re-designation of a portion of the second amount of the NVRAIVI for use as memory.

12. The device of claim 11 , comprising the hardware control logic to: provide access to at least one physical location in the NVRAIVI for a software application running on the computer system through the memory remap table, the memory remap table arranged to translate at least a platform physical address to a physical NVRAM address.

13. The device of claim 11 , comprising the storage remap table arranged to translate at least a logical block address to a physical NVRAM address.

14. The device of claim 11 , comprising the hardware control logic to: generate a page status table having at least a bit associated with separate NVRAM physical pages of the NRAM in separate page status table entries, the separate page status table entries indicating whether a given NVRAM physical page corresponding to a given page status table entry is designated for use as memory or storage.

15. The device of claim 11 , comprising: a write buffer logic to: determine, for separate NVRAM physical pages of a plurality of NVRAM physical pages, whether individual NVRAM physical pages are free to be written to, an individual NVRAM physical page is free to be written to when the individual NVRAM physical page is not holding valid data; determine, for separately identified free NVRAM physical pages, whether the separately identified free NVRAM physical pages are clean, wherein a given free NVRAM physical page is clean when all stored bits in the given free NVRAM physical page are set to one; and clean at least one separately identified free NVRAM physical page, wherein the at least one separately identified free NVRAM physical page to be cleaned includes at least one stored bit set to zero.

16. The device of claim 11 , comprising: the first amount of the NVRAM for use as memory includes arranging the first amount of the NVRAM to function as at least a portion of system memory for the computing system; and the second amount of the NVRAM for use as storage includes arranging the first amount of the NVRAM to function as mass storage for the computing system.

17. The device of claim 11 , wherein the NVRAM comprises at least one of phase change memory, phase change memory and switch (PCMS), resistive memory (RRAM), ferroelectric memory, spin-transfer torque random access memory (STRAM), spin tunneling random access memory (SPRAM), magnetoresistive memory, magnetic memory, magnetic random access memory (MRAM) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory.

18. A system, comprising: a non-volatile random access memory (NVRAM); a volatile random access memory; and a hardware control logic to: designate a first amount of the NVRAM for use as memory for a computing system; designate a second amount of the NVRAM for use as storage for the computing system; generate a memory remap table based on the first amount of the NVRAM designated for use as memory; generate a storage remap table based on the second amount of the NVRAM designated for use as storage; and update the memory and storage remap tables responsive to a first re-designation of a portion of the first amount of the NVRAM for use as storage or a second re-designation of a portion of the second amount of the NVRAM for use as memory.

19. The system of claim 18 , comprising the hardware control logic to: provide access to at least one physical location in the NVRAM for a software application running on the computer system through the memory remap table, the memory remap table arranged to translate at least a platform physical address to a physical NVRAM address.

20. The system of claim 18 , comprising the hardware control logic to: cause the memory and storage remap tables to be stored to the volatile random access memory, the volatile random access memory comprising dynamic random access memory (DRAM) or static random access memory (SRAM).

21. The system of claim 18 , comprising the storage remap table arranged to translate at least a logical block address to a physical NVRAM address.

22. The system of claim 18 , comprising the hardware control logic to: a page status table having at least a bit associated with separate NVRAM physical pages of the NRAM in separate page status table entries, the separate page status table entries indicating whether a given NVRAM physical page corresponding to a given page status table entry is designated for use as memory or storage; and cause the page status table to be stored to the NVRAM.

23. The system of claim 18 , comprising: a write buffer logic to: determine, for separate NVRAM physical pages of a plurality of NVRAM physical pages, whether individual NVRAM physical pages are free to be written to, an individual NVRAM physical page is free to be written to when the individual NVRAM physical page is not holding valid data; determine, for separately identified free NVRAM physical pages, whether the separately identified free NVRAM physical pages are clean, wherein a given free NVRAM physical page is clean when all stored bits in the given free NVRAM physical page are set to one; and clean at least one separately identified free NVRAM physical page, wherein the at least one separately identified free NVRAM physical page to be cleaned includes at least one stored bit set to zero.

24. The system of claim 18 , comprising the volatile random access memory arranged to function as a near memory for a multi-level memory and the first amount of the NVRAM designated for use as memory arranged as far memory for the multi-level memory.

25. The system of claim 24 , comprising: the multi-level memory arranged to function as system memory for the computing system; and the second amount of the NVRAM designated for use as storage includes the second amount of the NVRAM arranged to function as mass storage for the computing system.

26. The system of claim 18 , wherein the NVRAM comprises at least one of phase change memory, phase change memory and switch (PCMS), resistive memory (RRAM), ferroelectric memory, spin-transfer torque random access memory (STRAM), spin tunneling random access memory (SPRAM), magnetoresistive memory, magnetic memory, magnetic random access memory (MRAM) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory.