Display Device and Method of Driving the Same

1. A display device comprising: a display panel including gate and data lines that cross each other; a first control signal generation unit that generates a source output enable signal and a first gate output enable signal in synchronization with a data enable signal modulated according to a spread frequency clock signal; a second control signal generation unit that starts to count a number of clocks of a fixed-frequency clock signal at a point of time at which a logic high state of the source output enable signal ends, and outputs a second gate output enable signal when the counted number of the clocks becomes equal to a reference value, wherein the fixed-frequency clock signal is generated by a clock signal generation unit that is not influenced by the spread frequency clock signal; an output control unit that outputs the first gate output enable signal as a gate output enable signal when a status of a current frame is judged to be abnormal under which a charging time of a horizontal line overlaps an output time of image data of a next horizontal line if the second gate output enable signal is applied in the current frame, and outputs the second gate output enable signal as a gate output enable signal when a status of the current frame is judged to be normal under which the charging time of the horizontal line does not overlap the output time of image data of the next horizontal line if the second gate output enable signal is applied in the current frame; and a gate driving unit that controls an outputting of a gate signal to the gate line using the second gate output enable signal.

2. The display device of claim 1 , wherein the second control signal generation unit counts the number of clocks of the fixed-frequency clock signal from a point of time at which the logic high state of the source output enable signal ends to a point of time at which a logic high state of the first gate output enable signal starts, at each of n horizontal periods of an (m−1) th frame, m and n being positive integers; calculates the reference value by calculating an average of the numbers of clocks counted at every n horizontal periods; and generates the second gate output enable signal in an m th frame using the calculated reference value.

3. The display device of claim 1 , further comprising another clock signal generation unit that receives an input frequency clock signal having a fixed frequency, and modulates the input frequency clock signal according to a spread spectrum technique to generate the spread frequency clock signal having a periodically changed frequency.

4. A method of driving a display device, the method comprising: generating a source output enable signal and a first gate output enable signal in synchronization with a data enable signal modulated according to a spread frequency clock signal through a first control signal generation unit; starting a counting of a number of clocks of a fixed-frequency clock signal at a point of time at which a logic high state of the source output enable signal ends, and outputting a second gate output enable signal when the counted number of the clocks becomes equal to a reference value, through a second control signal generation unit, wherein the fixed-frequency clock signal is generated by a clock signal generation unit that is not influenced by the spread frequency clock signal; outputting the first gate output enable signal as a gate output enable signal when a status of a current frame is judged to be abnormal under which a charging time of a horizontal line overlaps an output time of image data of a next horizontal line if the second gate output enable signal is applied in the current frame, and outputting the second gate output enable signal as a gate output enable signal when a status of the current frame is judged to be normal under which the charging time of the horizontal line does not overlap the output time of image data of the next horizontal line if the second gate output enable signal is applied in the current frame, through an output control unit; and controlling an outputting of a gate signal from a gate driving unit to a display panel using the second gate output enable signal.

5. The method of claim 4 , wherein the outputting of the second gate output enable signal comprises: counting the number of clocks of the fixed-frequency clock signal from a point of time at which the logic high state of the source output enable signal ends to a point of time at which a logic high state of the first gate output enable signal starts, at each of n horizontal periods of an (m−1) th frame, wherein m and n are positive integers; calculating the reference value by calculating an average of the numbers of clocks counted at every n horizontal periods; and generating the second gate output enable signal in an m th frame using the calculated reference value.

6. The method of claim 4 , further comprising receiving an input frequency clock signal having a fixed frequency, and modulates the input frequency clock signal according to a spread spectrum technique to generate the spread frequency clock signal having a periodically changed frequency.

7. A display device comprising: a display panel including gate and data lines that cross each other; a first control signal generation unit that generates a source output enable signal and a first gate output enable signal in synchronization with a data enable signal modulated according to a spread frequency clock signal; a second control signal generation unit that starts to count a number of clocks of a fixed-frequency clock signal at a point of time at which a logic high state of the source output enable signal ends, and outputs a second gate output enable signal when the counted number of the clocks becomes equal to a reference value; an output control unit that outputs the first gate output enable signal as a gate output enable signal when a status of a current frame is judged to be abnormal under which a charging time of a horizontal line overlaps an output time of image data of a next horizontal line if the second gate output enable signal is applied in the current frame, and outputs the second gate output enable signal as a gate output enable signal when a status of the current frame is judged to be normal under which the charging time of the horizontal line does not overlap the output time of image data of the next horizontal line if the second gate output enable signal is applied in the current frame; and a gate driving unit that controls an outputting of a gate signal to the gate line using the gate output enable signal output from the output control unit.

8. The display device of claim 7 , wherein the status of the current frame is judged to be abnormal when a horizontal period of a first horizontal line of the current frame is less than a horizontal period set according to the reference value of the previous frame and the status of the current frame is judged to be normal when the horizontal period of the first horizontal line of the current frame is equal to or greater than the horizontal period set according to the reference value of the previous frame.

9. The display device of claim 7 , wherein the status of the current frame is judged to be abnormal when a frequency of a clock signal of a first horizontal line of the current frame is greater than a frequency set according to the reference value of the previous frame and the status of the current frame is judged to be normal when the frequency of the clock signal of the first horizontal line of the current frame is equal to or less than a frequency set according to the reference value of the previous frame.

10. The display device of claim 7 , wherein the second control signal generation unit counts the number of clocks of the fixed-frequency clock signal from a point of time at which the logic high state of the source output enable signal ends to a point of time at which a logic high state of the first gate output enable signal starts, at each of n horizontal periods of the previous frame, n being a positive integer; calculates the reference value by calculating an average of the numbers of clocks counted at every n horizontal periods; and generates the second gate output enable signal of the current frame using the calculated reference value.

11. The display device of claim 7 , further comprising a clock signal generation unit that receives an input frequency clock signal having a fixed frequency, and modulates the input frequency clock signal according to a spread spectrum technique to generate the spread frequency clock signal having a periodically changed frequency.

12. A method of driving a display device, comprising: generating a source output enable signal and a first gate output enable signal in synchronization with a data enable signal modulated according to a spread frequency clock signal through a first control signal generation unit; starting a counting of a number of clocks of a fixed-frequency clock signal at a point of time at which a logic high state of the source output enable signal ends, and outputting a second gate output enable signal when the counted number of the clocks becomes equal to a reference value, through a second control signal generation unit; outputting the first gate output enable signal as a gate output enable signal when a status of a current frame is judged to be abnormal under which a charging time of a horizontal line overlaps an output time of image data of a next horizontal line if the second gate output enable signal is applied in the current frame, and outputting the second gate output enable signal as a gate output enable signal when a status of the current frame is judged to be normal under which the charging time of the horizontal line does not overlap the output time of image data of the next horizontal line if the second gate output enable signal is applied in the current frame, through an output control unit; and controlling an outputting of a gate signal from a gate driving unit to a display panel using the gate output enable signal from the output control unit.

13. The method of claim 12 , wherein the status of the current frame is judged to be abnormal when a horizontal period of a first horizontal line of the current frame is less than a horizontal period set according to the reference value of the previous frame and the status of the current frame is judged to be normal when the horizontal period of the first horizontal line of the current frame is equal to or greater than the horizontal period set according to the reference value of the previous frame.

14. The method of claim 12 , wherein the status is judged to be abnormal when a frequency of a clock signal of a first horizontal line of the current frame is greater than a frequency set according to the reference value of the previous frame and the status of the current frame is judged to be normal when the frequency of the clock signal of the first horizontal line of the current frame is equal to or less than a frequency set according to the reference value of the previous frame.

15. The method of claim 12 , wherein the outputting of the second gate output enable signal comprises: counting the number of clocks of the fixed-frequency clock signal from a point of time at which the logic high state of the source output enable signal ends to a point of time at which a logic high state of the first gate output enable signal starts, at each of n horizontal periods of the previous frame, wherein n is a positive integer; calculating the reference value by calculating an average of the numbers of clocks counted at every n horizontal periods; and generating the second gate output enable signal of the current frame using the calculated reference value.

16. The method of claim 12 , further comprising receiving an input frequency clock signal having a fixed frequency, and modulating the input frequency clock signal according to a spread spectrum technique to generate the spread frequency clock signal having a periodically changed frequency.