Running State Power Saving via Reduced Instructions Per Clock Operation

1. A microprocessor configured to transition through a plurality of performance running states, ranging between lowest and highest, each comparatively characterized by differences in clock frequencies and/or voltage levels, the microprocessor comprising: functional units; and control registers, writeable to cause the functional units to institute one or more power-saving actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state; wherein the lowest performance running state comprises a non-sleeping state in which the microprocessor runs at its lowest supported clock frequency; wherein the microprocessor is configured with microcode to write the control registers to institute the one or more instructions-per-clock rate reducing actions, wherein the microcode is invoked in response to an instruction instructing the microprocessor to transition to the lowest performing running state.

2. The microprocessor of claim 1 , wherein the one or more actions comprise: the functional units switch from executing instructions out of program order to executing instructions in program order.

3. The microprocessor of claim 1 , wherein the functional units comprise an instruction issue unit, wherein the one or more power saving actions comprise: the instruction issue unit switches from issuing for execution multiple instructions per clock cycle to issuing only one instruction per clock cycle.

4. The microprocessor of claim 1 , wherein the functional units comprise an instruction retire unit, wherein the one or more power saving actions comprise: the retire unit switches from retiring multiple instructions per clock cycle to retiring a single instruction per clock cycle.

5. The microprocessor of claim 1 , wherein the functional units comprise an instruction format unit, wherein the one or more power saving actions comprise: the instruction format unit switches from formatting multiple instructions per clock cycle to formatting a single instruction per clock cycle from a stream of instruction bytes fetched from an instruction cache, wherein the stream comprises variable-length instructions, wherein said formatting comprises determining boundaries of the variable-length instructions within the stream.

6. The microprocessor of claim 1 , wherein the functional units comprise a memory subsystem, wherein the one or more power saving actions comprise: the memory subsystem switches from accessing a plurality of cache memories of the microprocessor in a parallel fashion to a serial fashion.

7. The microprocessor of claim 1 , wherein the functional units comprise an instruction translator, wherein the one or more power saving actions comprise: the instruction translator switches from translating multiple macroinstructions into microinstructions per clock cycle to translating a single macroinstruction into microinstructions per clock cycle.

8. The microprocessor of claim 1 , wherein the functional units comprise an instruction translator, wherein the one or more power saving actions comprise: the instruction translator disables instruction fusing during translation of macroinstructions into microinstructions.

9. A microprocessor configured to transition through a plurality of performance running states, ranging between lowest and highest, each comparatively characterized by differences in clock frequencies and/or voltage levels, the microprocessor comprising: functional units; and control registers, writeable to cause the functional units to institute one or more actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state, only if a predetermined condition exists, wherein the predetermined condition is a function of an amount of time the microprocessor ran in one or more performance states prior to a most recent transition to the lowest performance running state and/or a time the microprocessor ran in the lowest performance running state after the most recent transition to the lowest performance state; wherein the lowest performance running state comprises a non-sleeping state in which the microprocessor runs at its lowest supported clock frequency.

10. The microprocessor of claim 9 , wherein the predetermined condition is that prior to the most recent transition to the lowest performance running state, the microprocessor was running at a higher performance running state for no more than a predetermined time period.

11. The microprocessor of claim 10 , wherein the microprocessor has a predetermined time period for each of the plurality of higher performance running states.

12. The microprocessor of claim 9 , wherein the predetermined condition is that a calculated score is less than a predetermined score, wherein the calculated score is calculated based on a weighted average of time spent in each of a plurality of higher performance running states.

13. The microprocessor of claim 9 , wherein another predetermined condition is that the microprocessor has been in the lowest performance running state at least a predetermined percentage of time over a most recent predetermined time period.

14. The microprocessor of claim 9 , wherein another predetermined condition is that the microprocessor supports multiple performance running states.

15. The microprocessor of claim 9 , wherein another predetermined condition is that the microprocessor detects that an operating system running on the microprocessor supports multiple performance running states.

16. The microprocessor of claim 9 , wherein another predetermined condition is that a user of the microprocessor has not disabled said instituting the one or more power saving actions that reduce the instructions-per-clock rate of the microprocessor, in response to said receiving a command to enter the lowest performance running state.

17. A method for saving power consumption by a microprocessor configured to transition through a plurality of performance running states, ranging between lowest and highest, each comparatively characterized by differences in clock frequencies and/or voltage levels, the method comprising: receiving a command to enter a lowest performance running state of the microprocessor, wherein the lowest performance running state comprises a non-sleeping state in which the microprocessor is running at its lowest supported clock frequency; invoking microcode to write control registers to cause functional units of the microprocessor to institute one or more power-saving actions to that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption; and instituting the one or more power saving actions that reduce the instructions-per-clock rate of the microprocessor in response to said receiving the command to enter the lowest performance running state.

18. The method of claim 17 , wherein the one or more power saving actions comprises: switching from executing instructions out of program order to executing instructions in program order.

19. The method of claim 17 , wherein the one or more power saving actions comprises: switching from issuing for execution multiple instructions per clock cycle to issuing only one instruction per clock cycle.

20. The method of claim 17 , wherein the one or more power saving actions comprises: switching from retiring multiple instructions per clock cycle to retiring a single instruction per clock cycle.

21. The method of claim 17 , wherein the one or more power saving actions comprises: switching from formatting multiple instructions per clock cycle to formatting a single instruction per clock cycle from a stream of instruction bytes fetched from an instruction cache, wherein the stream comprises variable-length instructions, wherein said formatting comprises determining boundaries of the variable-length instructions within the stream.

22. The method of claim 17 , wherein the one or more power saving actions comprises: switching from accessing a plurality of cache memories of the microprocessor in a parallel fashion to a serial fashion.

23. The method of claim 17 , wherein the one or more power saving actions comprises: switching from translating multiple macroinstructions into microinstructions per clock cycle to translating a single macroinstruction into microinstructions per clock cycle.

24. The method of claim 17 , wherein the one or more power saving actions comprises: disabling instruction fusing during translation of macroinstructions into microinstructions.

25. The method of claim 17 , further comprising: determining whether at least one of a plurality of predetermined conditions exists, prior to said instituting the one or more power saving actions; wherein said instituting the one or more power saving actions is performed only if at least one of a plurality of predetermined conditions exists.

26. The method of claim 25 , wherein the plurality of predetermined conditions comprises: prior to the most recent transition to the lowest performance running state, the microprocessor was running at a higher performance running state for no more than a predetermined time period.

27. The method of claim 25 , wherein the plurality of predetermined conditions comprises: the microprocessor has been in the lowest performance running state at least a predetermined percentage of time over a most recent predetermined time period.

28. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising: computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising: first program code configuring the microprocessor to transition through a plurality of performance running states, ranging between lowest and highest, each comparatively characterized by differences in clock frequencies and/or voltage levels; second program code for specifying functional units; third program code for specifying control registers, writeable to cause the functional units to institute one or more power-saving actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state; wherein the lowest performance running state comprises a non-sleeping state in which the microprocessor runs at its lowest supported clock frequency; and further comprising fourth program code to write the control registers to institute the one or more instructions-per-clock rate reducing actions, wherein the fourth program code is invoked in response to an instruction instructing the microprocessor to transition to the lowest performing running state.