Shift Register Circuit and Shading Waveform Generating Method

1. A shift register circuit, comprising: a plurality of stages of shift registers, each of the plurality of stages of the shift registers comprising: an output transistor, having a first terminal, a second terminal and a gate terminal, the first terminal of the output transistor being configured to receive a first clock signal, the second terminal of the output transistor being configured for generating an output signal of a present stage of the shift register and providing the output signal to a next stage and/or a previous stage of the shift register; and a gate-shading circuit, comprising: a first transistor, having a first terminal, a second terminal and a gate terminal, the first terminal of the first transistor being configured for directly receiving a second clock signal, the gate terminal of the first transistor being directly electrically coupled to the gate terminal of the output transistor, receiving a voltage level of the gate terminal of the output transistor and being for controlling whether to conduct or cutoff between the first terminal and the second terminal of the first transistor according to the voltage level of the gate terminal of the output transistor; a second switch, having a first terminal, a second terminal and a gate terminal, wherein the first terminal of the second switch is electrically coupled to the gate terminal of the output transistor, the second terminal of the second switch is configured for receiving a first reference voltage and the gate terminal of the second switch is electrically coupled to the second terminal of the first transistor; and a third switch, having a first terminal, a second terminal and a gate terminal, wherein the first terminal of the third switch is electrically coupled to the second terminal of the output transistor, the second terminal of the third switch is configured for receiving a second reference voltage, and the gate terminal of the third switch is electrically coupled to the second terminal of the first transistor, wherein the first transistor is configured to control the second switch, in response to the second clock signal, to pull down the voltage level of the gate terminal of the output transistor from a boost voltage level, which is logically higher than a first voltage level turning on the output transistor.

2. The shift register circuit of claim 1 , further comprising an input unit configured for controlling the gate terminal of the output transistor, wherein the input unit is electrically coupled to the previous stage of the shift register, the output signal of the present stage of the shift register is provided to the next stage of the shift register, the shift register circuit is forward scan shifting.

3. The shift register circuit of claim 1 , further comprising an input unit configured for controlling the gate terminal of the output transistor, wherein the input unit is electrically coupled to the next stage of the shift register, the output signal of the present stage of the shift register is provided to the previous stage of the shift register, the shift register circuit is reverse scan shifting.

4. The shift register circuit of claim 1 , further comprising an input unit configured for controlling the gate terminal of the output transistor, wherein the input unit is electrically coupled to the previous stage and the next stage of the shift register.

5. The shift register circuit of claim 1 , wherein each of the plurality of stages of the shift registers further comprises a voltage stabilizing circuit electrically coupled to the gate terminal of the output transistor and the second terminal of the output transistor, wherein when the present stage of the shift register is not activated, the voltage stabilizing circuit is configured for maintaining the gate terminal of the output transistor and the output signal of the present stage of the shift register at a low voltage level.

6. The shift register circuit of claim 1 , wherein a pulse width of the second clock signal is positively correlated to a shading width of shading of the output signal.

7. The shift register circuit of claim 6 , wherein a shading slope rate of the output signal is positively correlated to a discharge capability, a voltage conversion rate and/or a conduction impedance of the second switch and the third switch.

8. The shift register circuit of claim 1 , wherein a shading slope rate of the output signal is positively correlated to a discharge capability, a voltage conversion rate and/or a conduction impedance of the second switch and the third switch.

9. The shift register circuit of claim 1 , wherein the second switch pulls down the voltage level of the gate terminal of the output transistor from the boost voltage level to form shading on the output signal.

10. The shift register circuit of claim 1 , wherein a wave width of the second clock signal is different from a wave width of the first clock signal.

11. A shift register circuit, comprising: a plurality of stages of shift registers, wherein each of the plurality of stages of the shift registers comprises: an output transistor, configured for generating an output signal of a present stage of the shift register on a second terminal of the output transistor according to a voltage level on a gate terminal of the output transistor and a voltage level on a first terminal of the output transistor; an input unit, electrically coupled to the output transistor and configured for controlling the voltage level on the gate terminal of the output transistor; a gate-shading circuit, comprising: a first transistor, directly electrically coupled to the gate terminal of the output transistor, receiving the voltage level on the gate terminal of the output transistor, and configured to output a control signal according to the voltage level on the gate terminal of the output transistor and a voltage level on a first terminal of the first transistor; a second switch, electrically coupled to the gate terminal of the output transistor and configured for pulling down the voltage level on the gate terminal of the output transistor according to the control signal; and a third switch, electrically coupled to the output transistor, and configured to pull down a voltage level on the second terminal of the output transistor according to the control signal, wherein the first terminal of the first transistor is directly receiving a second clock signal and is configured to control the second switch, in response to the second clock signal, to pull down the voltage level on the gate terminal of the output transistor from a boost voltage level, which is logically higher than a first voltage level turning on the output transistor; and a voltage stabilizing circuit, electrically coupled to the gate terminal of the output transistor and the second terminal of the output transistor, wherein when the present stage of the shift register is not activated, the voltage stabilizing circuit is configured for maintaining the gate terminal of the output transistor and the output signal of the present stage of the shift register at a low voltage level.

12. The shift register circuit of claim 11 , wherein the second switch has a first terminal, a second terminal and a gate terminal; the first terminal of the second switch is electrically coupled to the gate terminal of the output transistor, the second terminal of the second switch is configured for receiving a first reference voltage and the gate terminal of the second switch is configured to receive the control signal.

13. The shift register circuit of claim 12 , wherein the first transistor has a first terminal, a second terminal and a gate terminal; the first terminal of the first transistor is configured for receiving the second clock signal, the gate terminal of the first transistor is electrically coupled to the gate terminal of the output transistor for controlling whether to conduct or cutoff between the first terminal and the second terminal of the first transistor according to the voltage level on the gate terminal of the output transistor.

14. The shift register circuit of claim 13 , wherein the third switch has a first terminal, a second terminal and a gate terminal; the first terminal of the third switch is electrically coupled to the second terminal of the output transistor, the second terminal of the third switch is configured for receiving a second reference voltage, and the gate terminal of the third switch is electrically coupled to the second terminal of the first transistor.

15. The shift register circuit of claim 11 , wherein the first transistor has a first terminal, a second terminal and a gate terminal; the first terminal of the first transistor is configured for receiving a second clock signal, the gate terminal of the first transistor is electrically coupled to the gate terminal of the output transistor for controlling whether to conduct or cutoff between the first terminal and the second terminal of the first transistor according to the voltage level on the gate terminal of the output transistor.

16. The shift register circuit of claim 15 , wherein the third switch has a first terminal, a second terminal and a gate terminal; the first terminal of the third switch is electrically coupled to the second terminal of the output transistor, the second terminal of the third switch is configured for receiving a second reference voltage, and the gate terminal of the third switch is electrically coupled to the second terminal of the first transistor.

17. The shift register circuit of claim 11 , wherein a pulse width of the second clock signal is positively correlated to a shading width of shading of the output signal.

18. The shift register circuit of claim 17 , wherein a shading slope rate of the output signal is positively correlated to a discharge capability, a voltage conversion rate and/or a conduction impedance of the second switch and the third switch.

19. The shift register circuit of claim 11 , wherein a shading slope rate of the output signal is positively correlated to a discharge capability, a voltage conversion rate and/or a conduction impedance of the second switch and the third switch.

20. The shift register circuit of claim 11 , wherein a wave width of the second clock signal is different from a wave width of the first clock signal.

21. A shading waveform generating method, comprising: providing a shift register circuit comprising a plurality of stages of shift registers, wherein each of the plurality of stages of the shift registers comprises: an output transistor, configured for generating an output signal of a present stage of the shift register on a second terminal of the output transistor according to a voltage level on a gate terminal of the output transistor and a voltage level on a first terminal of the output transistor; an input unit, electrically coupled to the output transistor and configured for controlling the voltage level on the gate terminal of the output transistor; a gate-shading circuit, comprising: a first transistor, directly electrically coupled to the gate terminal of the output transistor, receiving the voltage level on the gate terminal of the output transistor, and configured to output a control signal according to the voltage level on the gate terminal of the output transistor and a voltage level on a first terminal of the first transistor; a second switch, electrically coupled to the gate terminal of the output transistor and configured for pulling down the voltage level on the gate terminal of the output transistor according to the control signal; and a third switch, electrically coupled to the output transistor, and configured to pull down a voltage level on the second terminal of the output transistor according to the control signal, wherein the first terminal of the first transistor is directly receiving a second clock signal and is configured to control the second switch, in response to the second clock signal, to pull down the voltage level of the gate terminal of the output transistor from a boost voltage level, which is logically higher than a first voltage level turning on the output transistor logic high level of the output signal, when the output signal is at the logic high level; and a voltage stabilizing circuit, electrically coupled to the gate terminal of the output transistor and the second terminal of the output transistor, wherein when the present stage of the shift register is not activated, and the voltage stabilizing circuit is configured for maintaining the gate terminal of the output transistor and the output signal of the present stage of the shift register at a low voltage level; turning on the output transistor of the present stage of the shift register and pulling up a voltage level of the second terminal of the output transistor through a first clock signal; turning on the second switch by the first transistor through the second clock signal to reduce a conductive degree of the output transistor; and turning on the third switch by the first transistor through the second clock signal.

22. The shading waveform generating method of claim 21 , comprising: increasing the gate terminal of the output transistor of the present stage of the shift register to a first voltage level through the output signal outputted by a previous stage of the shift register, to conduct the output transistor of the present stage of the shift register when the previous stage of the shift register is activated; and generating the output signal by transmitting the first clock signal through the output transistor to the second terminal of the output transistor when the present stage of the shift register is activated, and increasing the gate terminal of the output transistor from the first voltage level to a boost voltage level through a coupling capacitance.