Systems and Methods for Optimizing Executable Models for Hardware Synthesis

1. A method for extending hardware optimizations for a model of a system created in a modeling environment, the method comprising: accessing, from a memory of a first computer, the model, the model having executable semantics; identifying, by one or more processors of the first computer or a second computer, a plurality of sets of model elements of the model where the model elements of the plurality of sets are functionally equivalent with each other; determining, by the one or more processors of the first computer or the second computer, a maximum number of model elements in the plurality of sets; replacing, by the one or more processors of the first computer or the second computer, the model elements of the plurality of sets of the model that are functionally equivalent with shared model elements; inserting into the model for the plurality of sets serializer components and deserializer components; if a first number of model elements for a first set is equal to the maximum number of model elements in the plurality of sets, configuring, by the one or more processors of the first computer or the second computer, a first shared model element for the first set to execute at an execution rate; if a second number of model elements for a second set is less than the maximum number of model elements in the plurality of sets, configuring, by the one or more processors of the first computer or the second computer: a second shared model element for the second set to execute at the execution rate, and a respective serializer component and a respective deserializer component for the second set to maintain a synchronous execution of the second shared model element within the model.

2. The method of claim 1 where the execution rate satisfies an overclocking constraint.

3. The method of claim 2 where the overclocking constraint is user specified, or determined programmatically.

4. The method of claim 1 where the configuring the respective serializer component and the respective deserializer component for the second set includes: configuring the respective serializer component to introduce one or more idle cycles, and configuring the respective deserializer to remove the one or more idle cycles.

5. The method of claim 4 wherein the one or more idle cycles equals the first number of model elements of the first set less the second number of model elements of the second set.

6. The method of claim 4 wherein the one or more idle cycles are null values.

7. The method of claim 1 further comprising: configuring the second shared model element for the second set to execute when a control signal is at a determined value, where the configuring the respective serializer component and the respective deserializer component for the second set includes configuring the respective serializer component to generate the control signal.

8. The method of claim 7 wherein the respective serializer component for the second set converts a parallel input data into a serial data input stream, and sets the control signal as valid for a sequence of data elements of the serial data input stream equal to the second number of model elements in the second set.

9. The method of claim 8 wherein the configuring the respective serializer component and the respective deserializer component for the second set further includes configuring the deserializer component to receive the control signal, and discard one or more of the data elements when the control signal is at the determined value.

10. The method of claim 1 further comprising: generating a hardware description of the model.

11. The method of claim 10 wherein the hardware description is hardware description language (HDL) code that corresponds to at least one of VHDL code, Verilog code, and SystemC code.

12. A method for extending hardware optimizations for a model of a system created in a modeling environment, the method comprising: accessing, from a memory of a first computer, the model, the model having executable semantics; identifying, by one or more processors of the first computer or a second computer, a plurality of sets of model elements of the model where the model elements of the plurality of sets are functionally equivalent with each other; determining, by the one or more processors of the first computer or the second computer, a maximum number of model elements in the plurality of sets; replacing, by the one or more processors of the first computer or the second computer, the model elements of the plurality of sets that are functionally equivalent with shared model elements; inserting into the model for the plurality of sets serializer components and deserializer components; if a number of model elements for a set of the plurality of sets, is less than the maximum number, configuring, by the one or more processors of the first computer or the second computer a respective serializer component to introduce one or more idle cycles, and a respective deserializer component to remove the one or more idle cycles; and configuring, by the one or more processors of the first computer or the second computer, the serializer components and the deserializer components to operate at a given overclocking rate.

13. The method of claim 12 wherein the given overclocking rate satisfies a constraint.

14. The method of claim 13 wherein the constraint is user specified, or determined programmatically.

15. A method, for extending hardware optimizations for a model of a system created in a modeling environment, the method comprising: accessing, from a memory of a first computer, the model, the model having executable semantics, the model having a plurality of target model elements that receive parallel input data having a dimension, and perform a function on the parallel input data; determining, by one or more processors of the first computer or a second computer, a maximum dimension of the parallel input data received by the plurality of target model elements; inserting into the model for the plurality of target model elements a serializer component and a deserializer component; if the parallel input data for a first target model element is equal to the maximum dimension, configuring the first target model element to execute at an execution rate; if the parallel input data for a second target model element is less than the maximum dimension, configuring the second target model element to execute at the execution rate; and configuring a respective serializer component and a respective deserializer component for the second target model element to maintain a synchronous execution of a shared model element within the model.

16. The method of claim 15 where the configuring the respective serializer component and the respective deserializer component for the second target model element includes: configuring the respective serializer component to introduce one or more idle cycles, and configuring the respective deserializer to remove the one or more idle cycles.

17. The method of claim 16 wherein the one or more idle cycles equals a difference between the maximum dimension and a dimension of the parallel input data of the second target model element.

18. The method of claim 15 further comprising: configuring the second target model element to execute when a control signal is at a determined value, where the configuring the respective serializer component and the respective deserializer component for the second target model element includes configuring the respective serializer component to generate the control signal.

19. The method of claim 18 wherein the respective serializer component for the second target model element converts the parallel input data into a serial data input stream, and sets the control signal as valid for a sequence of data elements of the serial input data stream equal to the dimension of the parallel input data to the second target model element.

20. A method for extending hardware optimizations for a model of a system created in a modeling environment, the method comprising: accessing, from a memory of a first computer, the model, the model having executable semantics; identifying, by one or more processors of the first computer or a second computer, a first set of model elements of the model that are functionally equivalent with each other; replacing, by the one or more processors of the first computer or the second computer, the first set of model elements that are functionally equivalent with a first single shared model element; inserting a first serializer component into the model, the first serializer component converting first parallel data of a first data path to first serial data at a first rate; inserting a first deserializer component into the model, the first deserializer component converting the first serial data of the first data path back to the first parallel data; connecting the first serializer component and the first deserializer component to the first single shared model element; identifying a second set of model elements of the model that are functionally equivalent with each other, where the second set contains fewer elements than the first set; replacing the second set of model elements that are functionally equivalent with a second single shared model element; inserting a second serializer component into the model, the second serializer component converting second parallel data of a second data path to second serial data at a second rate; inserting a second deserializer component into the model, the second deserializer component converting the second serial data of the second data path back to the second parallel data; connecting the second serializer component and the second deserializer component to the second single shared model element; configuring the second serializer component to introduce one or more idle cycles into the second data path; and configuring the second deserializer component to remove the one or more idle cycles introduced into the second data path, where the second rate is equal to or less than the first rate.

21. The method of claim 20 further comprising: configuring the first serializer component to generate a first control signal that designates elements of the first parallel data converted by the first serializer component as either valid or invalid; and configuring the first serializer component to generate a second control signal that designates a first element of the first serial data as a start of a frame of the first parallel data.

22. The method of claim 20 further comprising: configuring the first deserializer component to receive a first control signal that designates elements of the first serial data as either valid or invalid; and configuring the first deserializer component to receive a second control signal that designates a first element of the first serial data as a start of a frame of the first parallel data.

23. The method of claim 20 wherein the model executes synchronously, and the one or more idle cycles maintain the synchronous execution of the model.

24. The method of claim 20 wherein the one or more idle cycles constrain an overclocking of the model to the first rate.

25. An apparatus for extending hardware optimizations for a model of a system created in a modeling environment, the apparatus comprising: a memory configured to store the model, the model having executable semantics; and one or more processors configured to: identify a plurality of sets of model elements of the model where the model elements of the plurality of sets are functionally equivalent with each other; determine a maximum number of model elements in the plurality of sets; replace the model elements of the plurality of sets that are functionally equivalent with shared model elements; insert into the model for the plurality of sets serializer components and deserializer components; utilize a respective serializer component to introduce one or more idle cycles and a respective deserializer component to remove the one or more idle cycles if a number of model elements, for a set of the plurality of sets, is less than the maximum number; and configure the serializer components and the deserializer components to operate at a given overclocking rate.

26. The apparatus of claim 25 wherein the given overclocking rate satisfies a constraint.

27. The apparatus of claim 26 wherein the constraint is user specified, or determined programmatically.

28. One or more non-transitory computer-readable media storing executable instructions for execution by processing logic hardware, the media storing one or more instructions for: accessing, from a memory, a model of a system created in a modeling environment, the model having executable semantics; identifying a plurality of sets of model elements of the model where the model elements of the plurality of sets are functionally equivalent with each other; determining, by the processing logic hardware, a maximum number of model elements in the plurality of sets; replacing, by the processing logic hardware, the model elements of the plurality of sets that are functionally equivalent with shared model elements; inserting into the model for the plurality of sets serializer components and deserializer components; configuring a respective serializer component to introduce one or more idle cycles and a respective deserializer component to remove the one or more idle cycles if a number of model elements, for a set of the plurality of sets, is less than the maximum number; and configuring the serializer components and the deserializer components to operate at a given overclocking rate.

29. The non-transitory computer-readable media of claim 28 wherein the given overclocking rate satisfies a constraint.

30. The non-transitory computer-readable media of claim 29 wherein the constraint is user specified, or determined programmatically.