Methods and Systems for Distributing Clock and Reset Signals Across An Address Macro

1. A distribution network for distributing clock and reset signals across an address macro, comprising: circuit blocks having dividers and counters, wherein the dividers and counters are synchronized relative to a clock signal; drivers connected in a balanced tree for distributing the clock signal synchronously to the circuit blocks, wherein the clock signal is gated before being inputted to the drivers connected in the balanced tree; drivers connected in an unbalanced tree for distributing a reset signal asynchronously to the circuit blocks; a logic gate for gating the clock signal to the drivers connected in the balanced tree; and a first counter, wherein the clock signal is inputted to the logic gate, wherein an output of the logic gate is connected to the balanced tree, wherein the logic gate enables the distribution of the clock signal to the balanced tree as a function of the reset signal, wherein the clock signal and the reset signal are inputted to the first counter, wherein the output of the first counter is inputted to the logic gate, wherein the clock signal is distributed via the balanced tree as a function of the reset signal, wherein, when the reset signal is activated, the clock signal is gated off from being inputted to the drivers connected in the balanced tree and the reset signal is asynchronously distributed to the circuit blocks via the drivers connected in the unbalanced tree, and wherein, when the reset signal is disabled, the clock signal is gated on after a first predefined number of clock cycles.

2. The distribution network of claim 1 wherein when the reset signal is activated, the first counter counts a second predefined number of clock cycles before the logic gate is gated off to block the clock signal from being distributed via the balanced tree.

3. The distribution network of claim 2 wherein when the reset signal is deactivated, the first counter counts the first predefined number of clock cycles before the logic gate is gated on to allow the clock signal to be distributed via the balanced tree.

4. The distribution network of claim 1 wherein the balanced tree is a binary tree.

5. The distribution network of claim 1 wherein the unbalanced tree is connected in a daisy-chain, wherein the reset signal is inputted to a certain one of the daisy-chained drivers of the unbalanced tree, and wherein the reset signal is further distributed by other ones of the daisy-chained drivers of the unbalanced tree.

6. A clock signal distribution network for distributing clock and reset signals across an address macro, comprising: circuit blocks having dividers and counters, wherein the dividers and counters are synchronized relative to a clock signal; drivers connected in a balanced tree for distributing the clock signal synchronously to the circuit blocks, wherein the clock signal is gated before being inputted to the drivers connected in the balanced tree; drivers connected in an unbalanced tree for distributing a reset signal asynchronously to the circuit blocks; a first counter; and an AND gate for gating the clock signal to the drivers connected in the balanced tree, wherein the clock signal and the reset signal are inputted to the first counter, wherein the output of the first counter is inputted to the AND gate, wherein the clock signal is distributed via the balanced tree as a function of the reset signal, wherein the clock signal is inputted to the AND gate, wherein an output of the AND gate is connected to the balanced tree, wherein the AND gate enables the distribution of the clock signal to the balanced tree as a function of the reset signal, wherein, when the reset signal is activated, the clock signal is gated off from being inputted to the drivers connected in the balanced tree and the reset signal is asynchronously distributed to the circuit blocks via the drivers connected in the unbalanced tree, and wherein, when the reset signal is disabled, the clock signal is gated on after a first predefined number of clock cycles.

7. The distribution network of claim 6 wherein when the reset signal is activated, the first counter counts a second predefined number of clock cycles before the AND gate is gated off to block the clock signal from being distributed via the balanced tree.

8. The distribution network of claim 7 wherein when the reset signal is deactivated, the first counter counts the first predefined number of clock cycles before the AND gate is gated on to allow the clock signal to be distributed via the balanced tree.

9. The distribution network of claim 6 wherein the balanced tree is a binary tree.

10. The distribution network of claim 6 wherein the unbalanced tree is connected in a daisy-chain, wherein the reset signal is inputted to a certain one of the daisy-chained drivers of the unbalanced tree, and wherein the reset signal is further distributed by other ones of the daisy-chained drivers of the unbalanced tree.

11. A clock signal distribution network, comprising: circuit blocks having counters, wherein the counters are synchronized relative to a clock signal; drivers connected in a balanced tree for distributing the clock signal synchronously to the circuit blocks, wherein the balanced tree is a binary tree; drivers connected in an unbalanced tree for distributing a reset signal to the circuit blocks, wherein the unbalanced tree is connected in a daisy-chain; a first counter; and an AND gate, wherein the clock signal and the reset signal are inputted to the first counter, wherein the output of the first counter is inputted to the AND gate, wherein the clock signal is distributed via the balanced tree as a function of the reset signal, wherein the clock signal is inputted to the AND gate, wherein an output of the AND gate is connected to the balanced tree, wherein the AND gate enables the distribution of the clock signal to the balanced tree as a function of the reset signal, wherein, when the reset signal is activated, the clock signal is gated off from being inputted to the drivers connected in the balanced tree and the reset signal is asynchronously distributed to the circuit blocks via the drivers connected in the unbalanced tree, and wherein, when the reset signal is disabled, the clock signal is gated on after a first predefined number of clock cycles.

12. The distribution network of claim 11 wherein when the reset signal is activated, the first counter counts a second predefined number of clock cycles before the AND gate is gated off to block the clock signal from being distributed via the balanced tree.

13. The distribution network of claim 12 wherein when the reset signal is deactivated, the first counter counts the first predefined number of clock cycles before the AND gate is gated on to allow the clock signal to be distributed via the balanced tree.

14. The distribution network of claim 11 wherein the reset signal is inputted to a certain one of the daisy-chained drivers of the unbalanced tree, and wherein the reset signal is further distributed by other ones of the daisy-chained drivers of the unbalanced tree.