9489183

Tile Communication Operator

PublishedNovember 8, 2016
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
18 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A computer readable memory storing computer-executable instructions that, when compiled and executed by a computer system, perform a method comprising: generating an output indexable type from an input indexable type in response to a tile communication operator in data parallel source code configured for execution on one or more data parallel optimal compute nodes having a special purpose architecture, the data parallel source code including data parallel features that take advantage of the special purpose architecture of the one or more data parallel optimal compute nodes to allow data parallel operations to be executed faster or more efficiently than with general purpose processors, the input indexable type defines a computational space of a data parallel algorithm and has a rank and at least one of a first element type and a first shape, the output indexable type has the rank and at least one of a second element type that is a tile of the input indexable type and a second shape that is a tile of the input indexable type; and performing the data parallel algorithm including a matrix operation using the output indexable type in which the output indexable type provides a local view structure of the computational space of the data parallel algorithm to enable coalescing of global memory accesses in the one or more data parallel optimal compute nodes.

2

2. The computer readable memory of claim 1 , wherein the input indexable type has the first element type, and wherein the output indexable type has the second element type that is a tile of the input indexable type.

3

3. The computer readable memory of claim 1 , wherein the input indexable type has the first shape, and wherein the output indexable type has the second shape that is a tile of the input indexable type.

4

4. The computer readable memory of claim 1 , wherein the output indexable type maps to an execution structure of the one or more data parallel optimal compute nodes.

5

5. The computer readable memory of claim 1 , wherein the data parallel source code is written in a high level general purpose programming language with data parallel extensions.

6

6. The computer readable memory of claim 1 , wherein the data parallel source code is written in a high level data parallel programming language.

7

7. The computer readable memory of claim 1 , wherein the one or more data parallel optimal compute nodes include at least one graphics processing unit.

8

8. The computer readable memory of claim 1 , wherein the one or more data parallel optimal compute nodes include at least one general purpose processor.

9

9. A method performed by a compiler in a computer system, the method comprising: identifying a tile communication operator in data parallel source code configured for execution on one or more data parallel optimal compute nodes having a special purpose architecture, the data parallel source code including data parallel features that take advantage of the special purpose architecture of the one or more data parallel optimal compute nodes to allow data parallel operations to be executed faster or more efficiently than with general purpose processors; and generating data parallel executable code from the data parallel source code such that the data parallel executable code implements tile communication operator by decomposing an input indexable type into an output indexable type for a matrix operation, the input indexable type defines a computational space of the data parallel executable code and has a rank and at least one of a first element type and a first shape, the output indexable type provides a local view structure of the computational space of the data parallel executable code to enable coalescing of global memory accesses in the one or more data parallel optimal compute nodes and has the rank and at least one of a second element type that is a tile of the input indexable type and a second shape that is a tile of the input indexable type.

10

10. The method of claim 9 wherein the input indexable type has the first element type, and wherein the output indexable type has the second element type that is a tile of the input indexable type.

11

11. The method of claim 9 , wherein the input indexable type has the first shape, and wherein the output indexable type has the second shape that is a tile of the input indexable type.

12

12. The method of claim 9 wherein the output indexable type maps to an execution structure of the one or more data parallel optimal compute nodes.

13

13. The method of claim 9 wherein the data parallel source code is written in a high level general purpose programming language with data parallel extensions.

14

14. The method of claim 9 wherein the data parallel source code is written in a high level data parallel programming language.

15

15. The method of claim 9 wherein the one or more data parallel optimal compute nodes include at least one graphics processing unit.

16

16. The method of claim 9 wherein the one or more data parallel optimal compute nodes include at least one general purpose processor.

17

17. A computer readable memory storing computer-executable instructions that, when executed by a computer system, perform a method comprising: applying a tile communication operator to decompose an input indexable type with a rank and a first element type into an output indexable type with the rank and a second element type that is a tile of the input indexable type; defining, with the input indexable type, a computational space of a data parallel algorithm; and performing the data parallel algorithm on the input indexable type using the output indexable type in a matrix operation in which the output indexable type provides a local view structure of the computational space of the data parallel algorithm to enable coalescing of global memory accesses in one or more data parallel optimal compute nodes; wherein the tile communications operator is included in data parallel source code written in a high level general purpose programming language with data parallel extensions, wherein the output indexable type maps to an execution structure of the one or more data parallel optimal compute nodes configured to perform the data parallel algorithm with a special purpose architecture, the data parallel extensions including data parallel features that take advantage of the special purpose architecture of the one or more data parallel optimal compute nodes to allow data parallel operations to be executed faster or more efficiently than with general purpose processors, and wherein the one or more data parallel optimal compute nodes include at least one graphics processing unit.

18

18. The computer readable memory of claim 17 , wherein the first element type has a first shape, and wherein the second element type has a second shape that is the tile.

Patent Metadata

Filing Date

Unknown

Publication Date

November 8, 2016

Inventors

Paul F. Ringseth

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Cite as: Patentable. “TILE COMMUNICATION OPERATOR” (9489183). https://patentable.app/patents/9489183

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