Multiple-Layer Configuration Storage for Runtime Reconfigurable Systems

1. A programmable logic device (PLD), comprising: a configuration bus; a plurality of programmable hardware units coupled to the configuration bus, each of the programmable hardware units configurable with one of a plurality of functional modes; a plurality of switch devices to independently select one or more configuration patterns from a set of configuration patterns, each of the switch devices corresponding to one of the programmable hardware units; a plurality of configuration registers coupled to the configuration bus and commonly shared by the plurality of programmable hardware units, the configuration registers storing the set of configuration patterns, where each configuration pattern corresponds to one of the plurality of functional modes of the programmable hardware units; a memory storing a set of index groups, each index group including a set of indices, configured to identify one of the plurality of configuration registers by selecting a corresponding select line on a corresponding one of the switch devices using a corresponding index in the set of indices; and one or more of the plurality of programmable hardware units accessing the configuration pattern, via the configuration bus, from the selected configuration register for configuration with the configuration pattern retrieved from the selected configuration register.

2. The PLD of claim 1 , wherein each of the switch devices is a multiplexer having a number of select lines equal to a number of configuration patterns.

3. The PLD of claim 1 , wherein the set of indices of one of the index groups is accessed to independently select, via an input line, a corresponding index associated with one or more of the plurality of switch devices to access the configuration registers for configuring the one or more plurality of programmable hardware units with a corresponding one of the plurality of functional modes.

4. The PLD of claim 1 , wherein the memory is addressed to read another set of indices of another one of the index groups to configure the one or more plurality of programmable hardware units with another one or more of the plurality of functional modes.

5. The PLD of claim 4 , wherein the one or more configuration patterns stored in the set of the configuration registers is exchanged with the updated configuration patterns when unused for a predetermined period.

6. The PLD of claim 1 , further comprising a runtime system controller to simultaneously schedule updating the configuration patterns in the plurality of configuration registers and access the configuration patterns from the plurality of configuration registers to configure the plurality of programmable hardware units.

7. The PLD of claim 6 , wherein one or more of the plurality of configuration registers are accessible at a same time by addressing one or more of the switching devices.

8. The PLD of claim 1 , further comprising a configuration storage comprising the plurality of configuration registers having a depth of a total number of the one or more functional modes of the plurality of programmable hardware units; and an index memory having a width of the number of the plurality of programmable hardware units multiplied by a number of bits to identify a depth D, where D=2 S , wherein the number of the plurality of programmable hardware units and the number of the plurality of switch devices are the same.

9. The PLD of claim 8 , wherein the number of configuration registers in the plurality of configuration registers is selected according a number of frequently used configuration patterns and a number of least frequently used configuration patterns, such that the total number of configuration registers is less than the total number of functional modes.

10. The PLD of claim 1 , wherein the programmable logic device is one of a FGPA, ASIC, SoC and EEPROM.

11. The PLD of claim 1 , wherein the total number of configurations patterns for the total number of programmable hardware units is equal to a depth of the index groups.

12. A method for configuring a programmable logic device (PLD), comprising: storing a set of configuration patterns in commonly shared configuration registers of a configuration memory such that each of the configuration patterns correspond to one or more functional modes of a plurality of programmable hardware units; independently selecting one or more configuration patterns from the set of configuration patterns using one or more switch devices, each of the switch devices corresponding to one of the programmable hardware units; storing, in an index memory, an index of addresses configured to identify one of a plurality of select lines of the switching device to address a corresponding one of the plurality of configuration registers; and accessing one of the configuration patterns by addressing the index memory to select one of the plurality of configuration registers to configure one of the programmable hardware units with the configuration pattern retrieved from the selected configuration register.

13. The method of claim 12 , wherein the configuration memory comprises static random access memory and the index memory comprises electrically erasable programmable read only memory.

14. The method of claim 12 , wherein each of the one or more switch devices is a multiplexer having a number of select lines equal to a number of configuration patterns.

15. The method of claim 12 , further comprising a controller sending an address to the configuration memory to read a group of indices, each of the indices in the group of indices corresponding to an input of each of the one or more switch devices.

16. The method of claim 12 , further comprising configuring one or more of the plurality of programmable hardware units by reading the one or more configuration patterns stored in at least one of the configuration registers; and simultaneously updating at least another one of the configuration registers with updated configuration patterns.

17. The method of claim 16 , further comprising exchanging the one or more configuration patterns stored in the at least another one of the configuration registers with the updated configuration patterns when unused for a predetermined period.

18. The method of claim 12 , further comprising, during runtime, simultaneously scheduling updates to the configuration patterns in the plurality of configuration registers; and accessing the configuration patterns from the plurality of configuration registers to configure the plurality of programmable hardware units.

19. The method of claim 18 , wherein one or more of the plurality of configuration registers are accessible at a same time by addressing one or more of the switching devices.

20. The method of claim 12 , wherein the configuration memory has a depth of a total number of the one or more functional modes of the plurality of programmable hardware units, and the index memory has a width of the number of the plurality of programmable hardware units multiplied by a number of bits to identify a depth D, where D=2 S , wherein the number of the plurality of programmable hardware units and the number of the plurality of switch devices are the same.

21. The method of claim 12 , further comprising providing a number of configuration registers in the plurality of configuration registers according a number of frequently used configuration patterns and a number of least frequently used configuration patterns, such that the total number of configuration registers is less than the total number of functional modes.

22. The method of claim 12 , wherein the programmable logic device is one of a FGPA, ASIC, SoC and EEPROM.

23. The method of claim 12 , wherein the total number of configurations patterns for the plurality of programmable hardware units is equal to a depth of the configuration memory.

24. A programmable logic device (PLD), comprising: a plurality of programmable hardware units configurable with one of a plurality of functional modes; a plurality of switch devices to select a configuration pattern from a set of configuration patterns, each of the switch devices corresponding to one of the programmable hardware units; a plurality of configuration registers commonly shared by the plurality of programmable hardware units, the configuration pattern corresponding to one of the plurality of functional modes; a memory storing a set of index groups configured to identify one of the plurality of configuration registers by selecting a corresponding select line on a corresponding one of the switch devices using a corresponding index from a set of indices in one of the index groups; and one or more of the plurality of programmable hardware units accessing the configuration pattern from the selected configuration register for configuration with the configuration pattern retrieved from the selected configuration register.

25. The PLD of claim 24 , further comprising a configuration bus coupling the plurality of programmable hardware units and the plurality of configuration registers, and wherein each of the switch devices corresponds to one of the programmable hardware units.

26. The PLD of claim 24 , wherein the configuration registers store the set of configuration patterns.

27. The PLD of claim 24 , further comprising a runtime system controller to simultaneously schedule updating the configuration pattern stored in each of the plurality of configuration registers and access the configuration patterns from the plurality of configuration registers to configure the plurality of programmable hardware units.