9542264

Memory System Monitoring Data Integrity and Related Method of Operation

PublishedJanuary 10, 2017
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
10 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A nonvolatile memory system, comprising: a nonvolatile memory comprising a plurality of pages; a buffer memory configured to temporarily store user data received from an external device; and a memory controller configured to write the user data into the nonvolatile memory or transmit read data to the external device according to a request from the external device, wherein the memory controller comprises: a host interface configured to receive the user data from the external device and to store the user data received from the external device in the buffer memory; a memory interface configured to receive the user data stored in the buffer memory and transmit the user data received from the buffer memory to the nonvolatile memory; a first data check engine configured to generate write data check information based on the user data received by the host interface; and a second data check engine configured to check integrity of the user data to be transmitted to the nonvolatile memory via the memory interface based on the generated write data check information, wherein the memory controller is configured to transmit the user data to be transmitted to the nonvolatile memory to the nonvolatile memory where the integrity of the user data to be transmitted to the nonvolatile memory is verified according to a check result of the second data check engine.

2

2. The nonvolatile memory system of claim 1 , wherein the write data check information comprises a logical block address of the user data and a cyclic redundancy check (CRC) code generated based on the user data.

3

3. The nonvolatile memory system of claim 1 , wherein each of the pages comprises a user area to store the user data and a spare area to store a logical page number.

4

4. The nonvolatile memory system of claim 3 , wherein a size of the user area is equal to a size of the user data or is an integer multiple of the size of the user data.

5

5. The nonvolatile memory system of in claim 3 , wherein the memory controller further comprises a logical block address calculator configured to calculate a logical block address of the user data stored in the user area based on the logical page number stored in the spare area.

6

6. The nonvolatile memory system of claim 5 , wherein the memory controller is configured to receive a read request from the external device and perform a read operation in response to the received read request, wherein the memory interface is configured to receive the user data stored in the user area and store the received user data in the buffer memory during the read operation, wherein the host interface is configured to receive the user data stored in the buffer memory and transmit the received user data to the external device, wherein the second data check engine is configured to generate read data check information based on the calculated logical block address and the user data received by the memory interface, and wherein the first check engine is configured to check the integrity of user data to be transmitted to the external device based on the read data check information where the user data is transmitted to the external device via the host interface.

7

7. The nonvolatile memory system of claim 5 , wherein the read data check information comprises a reference tag comprising a logical block address of the user data and a guard tag comprising a cyclic redundancy check (CRC) code for detecting an error of the user data.

8

8. The nonvolatile memory system of claim 7 , wherein the memory controller is configured to transmit the user data without the read data check information to the external device.

9

9. The nonvolatile memory system of claim 1 , wherein the write data check information comprises a reference tag comprising a logical block address of the user data and a guard tag comprising a cyclic redundancy check (CRC) code for detecting an error of the user data.

10

10. The nonvolatile memory system of claim 9 , wherein the memory controller is configured to transmit the user data without the read data check information to the nonvolatile memory.

Patent Metadata

Filing Date

Unknown

Publication Date

January 10, 2017

Inventors

KWANGSEOK IM
JUNG-YEON YOON
HAN-JU LEE
HA-NEUL JEONG

Want to explore more patents?

Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.

Citation & reuse

Analysis on this page is generated by Patentable — an AI-powered patent intelligence platform. AI-generated summaries, explanations, and analysis may be reused with attribution and a visible link back to the canonical URL below. Patent abstracts and claims are USPTO public domain.

Cite as: Patentable. “MEMORY SYSTEM MONITORING DATA INTEGRITY AND RELATED METHOD OF OPERATION” (9542264). https://patentable.app/patents/9542264

© 2026 Patentable. All rights reserved.

Patentable is a research and drafting-assistant tool, not a law firm, and does not provide legal advice. Documents we generate are drafts for review by a licensed patent attorney.

MEMORY SYSTEM MONITORING DATA INTEGRITY AND RELATED METHOD OF OPERATION — KWANGSEOK IM | Patentable