Switching Architecture with Packet Encapsulation

1. A system for passing Time Division Multiplexing (TDM) traffic through a packet switch, comprising: a packet switch having a plurality of data ports and being capable of routing Fixed Size Data Unit (FSDU) packets between the plurality of data ports; a TDM encapsulation circuit coupled to a data flow of TDM data and having a circuit demultiplexer for processing an incoming data flow of TDM data to buffer data associated with different TDM circuits into different buffer locations, a timer for monitoring a frame boundary, a FSDU generator for generating an FSDU and filling the generated FSDU with data associated with a respective one of the TDM circuits and for generating header information representative of information for allowing the packet switch to route the generated FSDU to a port associated with the respective one of the TDM circuits; and a jitter buffer for reducing variable delays arising from passing through the packet switch, wherein the jitter buffer has a size selected to maintain jitter below 125 microseconds.

2. A system according to claim 1 , further comprising: a merge circuit for merging the generated FSDU with packet flow data being sent to the packet switch.

3. A system according to claim 1 , further comprising: a decapsulation circuit for processing a generated FSDU passed through the packet switch to provide data to one or more TDM circuits sending data from a port of the packet switch.

4. A system according to claim 1 , wherein the circuit demultiplexer includes means for accessing a connection table having information representative of the ports associated with a circuit.

5. A system according to claim 1 , further including a priority switch for associating a routing priority level with a generated FSDU.

6. A system according to claim 5 , further comprising a bandwidth allocation process for allocating bandwidth for generated FSDU traffic to provide a predetermined latency period for routing traffic through the packet switch.

7. A system according to claim 1 , wherein the jitter buffer has a size selected as a function of a minimum and maximum latency for data passing through the packet switch.

8. A system according to claim 1 , wherein the packet switch includes ports capable of supporting a combination of traffic types.

9. A system according to claim 1 , wherein traffic types include packet type traffic and TDM type traffic.

10. A system according to claim 1 , further comprising a dropped-circuit detector for detecting a dropped TDM circuit.

11. A system according to claim 10 , wherein the FSDU generator responds to the dropped circuit detector to adjust the contents of the FSDU.

12. A process for passing Time Division Multiplexing (TDM) traffic through a packet switch having a plurality of data ports and being capable of routing Fixed Size Data Unit (FSDU) packets between the plurality of data ports, the process comprising; encapsulating a TDM data flow by sorting the TDM data flow into different respective buffer locations; generating an FSDU that can pass through the packet switch and filling the generated FSDU with data associated with a respective one of the TDM circuits; generating header information representative of information for routing the generated FSDU to a port associated with the respective one of the TDM circuits; combining the generated FSDU with a flow of packet data being sent to the packet switch; and with a jitter buffer, reducing variable delays arising from passing through the packet switch, wherein the jitter buffer has a size selected to maintain jitter below 125 microseconds.

13. A process according to claim 12 , further comprising processing a generated FSDU having been passed through the packet switch to reconstruct a TDM data flow circuit at an output port of the packet switch.

14. A process according to claim 13 , further comprising monitoring the number of TDM circuits within the TDM data flow to identify a change in the number of TDM circuits.

15. A process according to claim 14 , further comprising altering the contents of the generated FSDU as a function of a detected change in the number of circuits in the TDM data flow.

16. A process according to claim 12 , further comprising setting a timer to establish a time period for filling the generated FSDU.

17. A process according to claim 16 , wherein the time period is set to the TDM frame boundary period.

18. A process according to claim 12 , further comprising buffering a generated TDM circuit at an output port to reduce latency induced time variations.

19. The system of claim 1 , further comprising, a timer to establish a time period for filling the generated FSDU, wherein the time period is set to a TDM frame boundary period.

20. A process for passing Time Division Multiplexing (TDM) traffic through a packet switch having a plurality of data ports and being capable of routing Fixed Size Data Unit (FSDU) packets between the plurality of data ports, the process comprising; encapsulating a TDM data flow by sorting the TDM data flow into different respective buffer locations; generating an FSDU that can pass through the packet switch and filling the generated FSDU with data associated with a respective one of the TDM circuits; generating header information representative of information for routing the generated FSDU to a port associated with the respective one of the TDM circuits; combining the generated FSDU with a flow of packet data being sent to the packet switch; and setting a timer to establish a time period for filling the generated FSDU, wherein the time period is set to a TDM frame boundary period.