Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC)

1. A system-on-chip (SoC) comprising: an adapter adapted on a semiconductor die to communicate with a first component in a manner compatible with a peripheral component interconnect (PCI)-compliant protocol and to communicate with a first interface in a manner compatible with a second protocol; the first interface adapted on the semiconductor die to perform a conversion of a PCI-compliant transaction to a second transaction and perform address translation to translate between a re-locatable address and a fixed address; and an interconnect adapted on the semiconductor die to provide interconnection and routing of communications between the first interface and a plurality of heterogeneous resources, each of the plurality of heterogeneous resources including an intellectual property (IP) core and an interface logic, wherein the SoC is to operate in a manner compatible with the PCI-compliant protocol and the IP core is to operate in a manner compatible with the second protocol.

2. The SoC of claim 1 , wherein the first interface is to implement PCI-compliant enumeration, including translation of configuration cycles of the PCI-compliant protocol into a format for the second protocol.

3. The SoC of claim 1 , wherein the first interface is to perform the address translation to translate a re-locatable PCI-compliant address into an advanced extensible interface (AXI)/open core protocol (OCP) address.

4. The SoC of claim 1 , wherein the first interface is to perform operations that are common across the plurality of heterogeneous resources, and each interface logic is to perform operations that are specific to the corresponding IP core.

5. The SoC of claim 4 , wherein the interface logic includes control register functionality.

6. The SoC of claim 5 , wherein the control register functionality enables the interface logic to power off the corresponding IP core.

7. The SoC of claim 1 , wherein the first interface and the interface logic provide a separated transaction-physical protocol.

8. The SoC of claim 7 , wherein the IP core of each of the plurality of heterogeneous resources does not include a physical unit.

9. The SoC of claim 8 , further comprising a physical unit coupled between a corresponding interface logic and the interconnect.

10. The SoC of claim 1 , wherein the first interface includes decode logic to perform a target decode for the plurality of heterogeneous resources.

11. The SoC of claim 1 , wherein the interconnect comprises a transaction-level modular interconnect.

12. The SoC of claim 1 , wherein the first component comprises a processor, and at least some of the plurality of heterogeneous resources are according to an advanced extensible interface (AXI)/open core protocol (OCP) technology.

13. A system comprising: a processor; a host interface coupled to the processor, the host interface to couple the processor to a memory; an adapter coupled to the host interface to communicate with the host interface according to a peripheral component interconnect (PCI)-compliant protocol and to communicate with a second interface according to a non-PCI-compliant protocol; the second interface coupled to the adapter and to perform a conversion of a transaction from the adapter to a second transaction and to perform address translation between a re-locatable address and a fixed address; and a first physical unit coupled between the second interface and an interconnect to communicate transactions between the second interface and the interconnect, wherein the interconnect is to couple the second interface to a plurality of second physical units each to couple to one of a plurality of heterogeneous resources, each of the plurality of heterogeneous resources including an intellectual property (IP) core and an interface logic, wherein the system is to operate in accordance with the PCI-compliant protocol and the IP core is to operate in accordance with the non-PCI-compliant protocol.

14. The system of claim 13 , wherein the system comprises an ultra mobile system and the processor is to execute a personal computer-based operating system.

15. The system of claim 14 , wherein the second interface is to translate configuration cycles of the PCI-compliant protocol into a format for the non-PCI-compliant protocol and to perform the address translation to translate a re-locatable peripheral component interconnect (PCI) address into an advanced extensible interface/open core protocol (AXI/OCP) address.

16. The system of claim 15 , wherein the second interface is to perform operations that are common across the plurality of heterogeneous resources, and each interface logic is to perform operations that are specific to the corresponding IP core, the common operations including the address translation and ordering of transactions, and the specific operations including power management and error handling.

17. A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising: converting a peripheral component interconnect (PCI) transaction having a format for a PCI protocol to a transaction having a format for a non-PCI protocol and performing an address translation between a re-locatable address and a fixed address for an intellectual property (IP) core that operates according to the second protocol, via a first interface; communicating the transaction between the first interface and an interconnect via a first physical unit coupled between the first interface and the interconnect; and implementing a PCI header of the PCI protocol for the IP core via an interface logic coupled to the interconnect.

18. The machine-readable medium of claim 17 , wherein the method further comprises translating configuration cycles of the PCI protocol into the format for the non-PCI protocol via the first interface.

19. The machine-readable medium of claim 17 , wherein the method further comprises performing the address translation to translate a re-locatable PCI address into a second address format.

20. The machine-readable medium of claim 17 , wherein the method further comprises performing operations that are common across a plurality of heterogeneous resources each having an IP core and a corresponding interface logic via the first interface, wherein each interface logic is to perform operations that are specific to the corresponding heterogeneous resource.