Semiconductor Device

1. A semiconductor device comprising: a gate signal line; a first gate driver circuit comprising first to sixth transistors; and a second gate driver circuit comprising seventh to twelfth transistors, wherein the gate signal line is electrically connected to a first terminal of the first transistor and a first terminal of the second transistor, wherein a gate of the first transistor is electrically connected to a first terminal of the third transistor and a first terminal of the fourth transistor, wherein a gate of the second transistor is directly connected to a first terminal of the fifth transistor and a first terminal of the sixth transistor, wherein a second terminal of the sixth transistor is directly connected to the gate of the first transistor, wherein the gate signal line is directly connected to a first terminal of the seventh transistor and a first terminal of the eighth transistor, wherein a gate of the seventh transistor is electrically connected to a first terminal of the ninth transistor and a first terminal of the tenth transistor, wherein a gate of the eighth transistor is directly connected to a first terminal of the eleventh transistor and a first terminal of the twelfth transistor, and wherein a second terminal of the twelfth transistor is directly connected to the gate of the seventh transistor.

2. The semiconductor device according to claim 1 , wherein the third transistor is diode-connected.

3. The semiconductor device according to claim 1 , wherein the fourth transistor is diode-connected.

4. The semiconductor device according to claim 1 , wherein the fifth transistor is diode-connected.

5. The semiconductor device according to claim 1 , wherein the sixth transistor is diode-connected.

6. The semiconductor device according to claim 1 , further comprising a pixel portion including a plurality of pixels between the first gate driver circuit and the second gate driver circuit.

7. The semiconductor device according to claim 1 , wherein the first gate driver circuit and the second gate driver circuit are provided on the same side of a pixel portion.

8. The semiconductor device according to claim 1 , wherein each of the first to twelfth transistors comprises an oxide semiconductor layer in which a channel formation region is formed.

9. A semiconductor device comprising: a gate signal line; and first to twelfth transistors, wherein the gate signal line is electrically connected to a first terminal of the first transistor and a first terminal of the second transistor, wherein a gate of the first transistor is electrically connected to a first terminal of the third transistor and a first terminal of the fourth transistor, wherein a gate of the second transistor is directly connected to a first terminal of the fifth transistor and a first terminal of the sixth transistor, wherein a second terminal of the sixth transistor is directly connected to the gate of the first transistor, wherein the gate signal line is directly connected to a first terminal of the seventh transistor and a first terminal of the eighth transistor, wherein a gate of the seventh transistor is electrically connected to a first terminal of the ninth transistor and a first terminal of the tenth transistor, wherein a gate of the eighth transistor is directly connected to a first terminal of the eleventh transistor and a first terminal of the twelfth transistor, and wherein a second terminal of the twelfth transistor is directly connected to the gate of the seventh transistor.

10. The semiconductor device according to claim 9 , wherein the third transistor is diode-connected.

11. The semiconductor device according to claim 9 , wherein the fourth transistor is diode-connected.

12. The semiconductor device according to claim 9 , wherein the fifth transistor is diode-connected.

13. The semiconductor device according to claim 9 , wherein the sixth transistor is diode-connected.

14. The semiconductor device according to claim 9 , wherein each of the first to twelfth transistors comprises an oxide semiconductor layer in which a channel formation region is formed.