Shift Register Unit, Gate Driving Circuit, and Display Device Comprising the Same

1. A shift register unit, comprising: a pull-up module configured to output a pulled up high level signal at a present-stage signal output according to signals from a pull-up control node and a first clock input; a control module connected to a first voltage terminal and a second voltage terminal and configured to control the level at the pull-up control node according to signals from a first signal input and a second clock input; and a reset module configured to reset the high level signal outputted from the present-stage signal output to a low level signal according to a signal from a second signal input, wherein the pull-up module comprises: a first transistor, of which the source is connected to the present-stage signal output, the gate is connected to the pull-up control node, and the drain is connected to the first clock input; and a capacitor connected between the source and the drain of the first transistor, wherein the control module comprises a first control sub-module and a second control sub-module, and wherein when the signal from the first signal input and the signal from the second clock input are both at high level, the pull-up control node is pulled up to high level; when the pull-up control node is at high level and the signal from the first clock input is at low level, the capacitor is pre-charged, so that when the signal from the first signal input and the signal from the second clock input are both in low level, the pull-up control node is maintained at high level by the second control sub-module according to the feedback signal, which is at high level, from the pull-up control node; and when the signal from the first signal input is at low level while the signal of the second clock input is a high level signal, the pull-up control node is switched to low level, and the pull-up control node is held at low level by the second control sub-module according to the feedback signal , which is at low level, from the pull-up control node.

2. The shift register unit according to claim 1 , wherein the first control sub-module comprises: a second transistor, of which the source is connected to a first pull-down control node, the gate is connected to the second clock input, and the drain is connected to the first signal input; and the second control sub-module comprises: a third transistor, of which the source is connected to the first pull-down control node, the gate and the drain both are connected to the second voltage terminal; a fourth transistor, of which the drain is connected to the first pull-down control node, the gate is connected to the pull-up control node, and the source is connected to the first voltage terminal; and a fifth transistor, of which the source is connected to the first voltage terminal, the gate is connected to the first pull-down control node, and the drain is connected to the pull-up control node.

3. The shift register unit according to claim 1 , wherein the reset module comprises: a sixth transistor, of which the source is connected to the first voltage terminal, the gate is connected to the second signal input, and the drain is connected to the present-stage signal output.

4. The shift register unit according to claim 1 , further comprising: a discharge module configured to control the pull-up module to discharge based on the signal outputted from the present-stage signal output.

5. The shift register unit according to claim 4 , wherein the discharge module comprises: a seventh transistor, of which the source is connected to a second pull-down control node, the gate and the drain are connected to the second voltage terminal; an eighth transistor, of which the source is connected to the first voltage terminal, the gate is connected to the present-stage signal output, and the drain is connected to the second pull-down control node; and a ninth transistor, of which the source is connected to the first voltage terminal, the gate is connected to the second pull-down control node, and the drain is connected to the present-stage signal output.

6. A gate driving circuit, comprising a plurality of shift register units according to claim 1 , wherein the present-stage output of each shift register unit except first-stage shift register unit is connected to the second signal input of an adjacent previous-stage shift register unit; the present-stage output of each shift register unit except last-stage shift register unit is connected to the first signal input of an adjacent next-stage shift register unit.

7. The gate driving circuit according to claim 6 , wherein the first control sub-module comprises: a second transistor, of which the source is connected to a first pull-down control node, the gate is connected to the second clock input, and the drain is connected to the first signal input; and the second control sub-module comprises: a third transistor, of which the source is connected to the first pull-down control node, the gate and the drain both are connected to the second voltage terminal; a fourth transistor, of which the drain is connected to the first pull-down control node, the gate is connected to the pull-up control node, and the source is connected to the first voltage terminal; and a fifth transistor, of which the source is connected to the first voltage terminal, the gate is connected to the first pull-down control node, and the drain is connected to the pull-up control node.

8. The gate driving circuit according to claim 6 , wherein the reset module comprises: a sixth transistor, of which the source is connected to the first voltage terminal, the gate is connected to the second signal input, and the drain is connected to the present-stage signal output.

9. The gate driving circuit according to claim 6 , further comprising: a discharge module configured to control the pull-up module to discharge based on the signal outputted from the present-stage signal output.

10. The gate driving circuit according to claim 9 , wherein the discharge module comprises: a seventh transistor, of which the source is connected to a second pull-down control node, the gate and the drain are connected to the second voltage terminal; an eighth transistor, of which the source is connected to the first voltage terminal, the gate is connected to the present-stage signal output, and the drain is connected to the second pull-down control node; and a ninth transistor, of which the source is connected to the first voltage terminal, the gate is connected to the second pull-down control node, and the drain is connected to the present-stage signal output.

11. The gate driving circuit according to claim 6 , wherein a frame start signal is inputted to the first signal input of the first-stage shift register unit, and a reset signal is inputted to the second signal input of the last-stage shift register unit.

12. A display device, comprising the gate driving circuit according to claim 6 .

13. The display device according to claim 12 , further comprising: a discharge module configured to control the pull-up module to discharge according to the signal outputted from the present-stage signal output.

14. The display device according to claim 12 , wherein a frame start signal is inputted to the first signal input of the first-stage shift register unit, and a reset signal is inputted to the second signal input of the last-stage shift register unit.