Gate Driving Circuit and Display Device

1. A gate driving circuit in a display device, comprising: a plurality of shift register units; a plurality of enable circuits, each connecting to an associated shift register unit and driving two associated gate lines; a logic circuit configured to receive a first clock signal (CLK 1 ), a second clock signal (CLK 2 ), a third clock signal (CLK 3 ) and a fourth clock signal (CLK 4 ), and output a first logic signal, a second logic signal, a third logic signal, a fourth logic signal, and a fifth logic signal; wherein the plurality of shift register units comprises: a first shift register unit configured to receive the first logic signal, a second shift register unit configured to receive the second logic signal, a third shift register unit configured to receive the third logic signal, and a fourth shift register unit configured to receive the fourth logic signal, wherein the plurality of enable circuits comprises, a first enable circuit connected with the first shift register unit and configured to receive the third logic signal and the fifth logic signal, a second enable circuit connected with the second shift register unit and configured to receive the fourth logic signal and the fifth logic signal, a third enable circuit connected with the third shift register unit and configured to receive the first logic signal and the fifth logic signal, and a fourth enable circuit connected with the fourth shift register unit and configured to receive the second logic signal and the fifth logic signal.

2. The gate driving circuit of claim 1 , wherein: each of the plurality of enable circuits outputs a first output signal and a second output signal, the pulse duration of the first output signal is equal to the pulse duration of the second output signal.

3. The gate driving circuit of claim 1 , wherein, the plurality of shift register units comprises a first set of cascaded shift register units and a second set of cascaded shift register units opposite to the first set of cascaded shift register units.

4. The gate driving circuit of claim 3 , wherein the first set of cascaded shift register units comprises a plurality of first shift register units and a plurality of third shift register units; and the second set of cascaded shift register units comprises a plurality of second shift register units and a plurality of fourth shift register units.

5. The gate driving circuit of claim 1 , wherein each of the enable circuits comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a fifth invertor and a sixth inverter; wherein: a source electrode of the first thin film transistor is connected, via the fifth invertor, with an output end of the shift register unit connected with the enable circuit, and a drain electrode of the first thin film transistor is connected with a source electrode of the third thin film transistor, a source of the second thin film transistor and a source electrode of the fifth thin film transistor; the source electrode of the second thin film transistor is configured to receive a high level signal, and a drain electrode of the second thin film transistor is connected with the drain electrode of the first thin film transistor; in the case of an enable circuit connected with an odd stage of shift register units from the first set of N stages of shift register units, a gate electrode of the first thin film transistor and a gate electrode of the second thin film transistor are configured to receive the inverted first logic pulse signal; in the case of an enable circuit connected with an odd stage of shift register units from the second set of N stages of shift register units, the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor are configured to receive the inverted second logic pulse signal; in the case of an enable circuit connected with an even stage of shift register units from the first set of N stages of shift register units, the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor are configured to receive the inverted third logic pulse signal; and in the case of an enable circuit connected with an even stage of shift register units from the second set of N stages of shift register units, the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor are configured to receive the inverted fourth logic pulse signal; the source electrode of the third thin film transistor is connected with the drain electrode of the first thin film transistor, a drain electrode of the third thin film transistor is connected with one of two output terminals of the enable circuit, and a gate electrode of the third thin film transistor is configured to receive the fifth logic pulse signal; a source electrode of the fourth thin film transistor is configured to receive a high level, a drain electrode of the fourth thin film transistor is connected with said one of the two output terminals of the enable circuit, and a gate electrode of the fourth thin film transistor is configured to receive the fifth logic pulse signal via the sixth inverter; the source electrode of the fifth thin film transistor is connected with the drain electrode of the first thin film transistor, a drain electrode of the fifth thin film transistor is connected with the other of the two output terminals of the enable circuit, and a gate electrode of the fifth thin film transistor is configured to receive the fifth logic pulse signal; and a source electrode of the sixth thin film transistor is configured to receive a high level signal, a drain electrode of the sixth thin film transistor is connected with the other of the two output terminals of the enable circuit, and a gate electrode of the sixth thin film transistor is configured to receive the fifth logic pulse signal.

6. The gate driving circuit of claim 1 , wherein the first logic signal is equal to CLK 1 * CLK 4 , the second logic signal is equal to CLK 2 * CLK 1 , the third logic signal is equal to CLK 3 * CLK 2 , the fourth logic signal is equal to CLK 4 * CLK 3 , and the fifth logic signal is equal to CLK 1 +CLK 3 + CLK 2 +CLK 4 , wherein the operator − represents a logic invert operation, the operator * represents a logic AND operation, and the operator + represents a logic OR operation.

7. The gate driving circuit of claim 1 , wherein when the third logic signal and the fifth logic signal are at a first logical level, the first enable circuit drives one of the respective two gate lines, when the third logic signal is at the first logic level and the fifth logic signal is at a second logical level, the first enable circuit drives the other one of the respective two gate lines; when the fourth logic signal and the fifth logic signal are at the first logical level, the second enable circuit drives one of the respective two gate lines, when the fourth logic signal is at the first logic level and the fifth logic signal is at the second logical level, the second enable circuit drives the other one of the respective two gate lines; when the first logic signal and the fifth logic signal are at the first logical level, the third enable circuit drives one of the respective two gate lines, when the first logic signal is at the first logic level and the fifth logic signal is at the second logical level, the third enable circuit drives the other one of the respective two gate lines; and when the second logic signal and the fifth logic signal are at the first logical level, the fourth enable circuit drives one of the respective two gate lines, when the second logic signal is at the first logic level and the fifth logic signal is at the second logical level, the fourth enable circuit drives the other one of the respective two gate lines.

8. The gate driving circuit of claim 1 , wherein the first logical level is one of a high level and a low level, and the second logical level is the other one of the high level and the low level.

9. A display device comprising: a display region comprising a plurality of pixels for displaying images; a gate driving circuit configured to transfer scanning signals to the display region; and a data driving circuit configured to transfer data signals to the display region; wherein the gate driving circuit comprises: a plurality of shift register units; a plurality of enable circuits, each connecting to an associated shift register unit and driving two associated gate lines; a logic circuit configured to receive a first clock signal (CLK 1 ), a second clock signal (CLK 2 ), a third clock signal (CLK 3 ) and a fourth clock signal (CLK 4 ), and output a first logic signal, a second logic signal, a third logic signal, a fourth logic signal and a fifth logic signal; wherein the plurality of shift register units comprises, a first shift register unit configured to receive the first logic signal; a second shift register unit configured to receive the second logic signal, a third shift register unit configured to receive the third logic signal, and a fourth shift register unit configured to receive the fourth logic signal, wherein the plurality of enable circuits comprises, a first enable circuit connected with the first shift register unit and configured to receive the third logic signal and the fifth logic signal, a second enable circuit connected with the second shift register unit and configured to receive the fourth logic signal and the fifth logic signal, a third enable circuit connected with the third shift register unit and configured to receive the first logic signal and the fifth logic signal, and a fourth enable circuit connected with the fourth shift register unit and configured to receive the second logic signal and the fifth logic signal.

10. The display device of claim 9 , wherein each of the plurality of enable circuits outputs a first output signal and a second output signal, the pulse duration of the first output signal is equal to the pulse duration of the second output signal.

11. The display device of claim 9 , wherein the plurality of shift register units comprise a first set of cascaded shift register units and a second set of cascaded shift register units opposite to the first set of cascaded shift register units.

12. The display device of claim 11 , wherein the first set of cascaded shift register units comprises a plurality of first shift register units and a plurality of third shift register units; and the second set of cascaded shift register units comprises a plurality of second shift register units and a plurality of fourth shift register units.