Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated clock gating cell, comprising: a logic gate, including a first input to receive an unbuffered enable signal (E), a second input to receive a scan test enable signal (SE), and an output that generates an inverted enable signal (EN); a first transmission gate, including a first terminal for receiving E, a second terminal for receiving SE, a third terminal for receiving EN, a fourth terminal, and a fifth terminal; a second transmission gate, including a first terminal connected to the fourth terminal of the first transmission gate, a second terminal connected to the fifth terminal of the first transmission gate, a third terminal for receiving a clock signal (CK), a fourth terminal for receiving an enabled and inverted clock signal (ECKN), and a fifth terminal; and a first transistor, including a first terminal connected to a power supply voltage (VDD), a second terminal connected to the output of the logic gate, and a third terminal connected to the fourth terminal of the first transmission gate; a second transistor, including a first terminal connected to the fifth terminal of the first transmission gate, a second terminal connected to VDD, and a third terminal; and a latch, including a first terminal connected to the fifth terminal of the second transmission gate, a second terminal connected to the third terminal of the second transistor, and a third terminal.
2. The integrated clock gating cell of claim 1 , wherein the logic gate is a NOR gate.
3. The integrated clock gating cell of claim 1 , wherein the first transistor is a p-channel metal oxide semiconductor (PMOS) transistor and the second transistor is an n-channel metal oxide semiconductor (NMOS) transistor.
4. The integrated clock gating cell of claim 1 , wherein the first and third terminals of the first transistor and the second transistor are either a source terminal or a drain terminal, and wherein the second terminal of the first transistor and the second transistor are each a gate terminal.
5. The integrated clock gating cell of claim 1 , wherein the first transmission gate is comprised of: a third transistor, including a first terminal for receiving E, a second terminal for receiving SE, and a third terminal; and a fourth transistor, including a first terminal, a second terminal for receiving EN, and a third terminal connected to the first terminal of the third transistor.
6. The integrated clock gating cell of claim 5 , wherein the third transistor is a p-channel metal oxide semiconductor (PMOS) transistor and the fourth transistor is an n-channel metal oxide semiconductor (NMOS) transistor.
7. The integrated clock gating cell of claim 5 , wherein the first and third terminals of the third transistor and the fourth transistor are either a source terminal or a drain terminal, and wherein the second terminal of the third transistor and the fourth transistor are each a gate terminal.
8. The integrated clock gating cell of claim 1 , wherein the second transmission gate is comprised of: a fifth transistor, including a first terminal connected to the third terminal of the third transistor, a second terminal for receiving a clock signal (CK), and a third terminal; a sixth transistor, including a first terminal connected to the first terminal of the fourth transistor, a second terminal for receiving an enabled clock signal (ECKN), and a third terminal connected to the third terminal of the fifth transistor.
9. The integrated clock gating cell of claim 8 , wherein the fifth transistor is a p-channel metal oxide semiconductor (PMOS) transistor and the sixth transistor is an n-channel metal oxide semiconductor (NMOS) transistor.
10. The integrated clock gating cell of claim 1 , wherein the first and third terminals of the fifth transistor and the sixth transistor are either a source terminal or a drain terminal, and wherein the second terminal of the fifth transistor and the sixth transistor are each a gate terminal.
11. The integrated clock gating cell of claim 1 , wherein the latch is comprised of: a third transistor, including a first terminal, a second terminal connected to the fifth terminal of the second transmission gate, and a third terminal connected to the third terminal of the second transistor; a fourth transistor, including a first terminal connected to VDD, a second terminal for receiving ECKN, and a third terminal connected to the fifth terminal of the second transmission gate; a fifth transistor, including a first terminal connected to VDD, a second terminal connected to the fifth terminal of the second transmission gate, and a third terminal connected to the first terminal of the third transistor; a sixth transistor, including a first terminal connected to VDD, a second terminal for receiving CK, and a third terminal connected to the first terminal of the third transistor; a seventh transistor, including a first terminal connected to the third terminal of the third transistor, a second terminal for receiving CK, and a third terminal connected to a ground; and an inverter, including an input connected to the third terminal of the tenth transistor, and an output for generating an enabled clock signal (ECK).
12. The integrated clock gating cell of claim 11 , wherein the fourth transistor, the fifth transistor, and the sixth transistor are each a p-channel metal oxide semiconductor (PMOS) transistor and the seventh transistor and the eleventh transistor are each an n-channel metal oxide semiconductor (NMOS) transistor.
13. The integrated clock gating cell of claim 11 , wherein the first and third terminals of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are either a source terminal or a drain terminal, and wherein the second terminal of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are each a gate terminal.
14. An integrated clock gating cell, comprising: a logic gate, including a first input to receive an unbuffered enable signal (E), a second input to receive a scan test enable signal (SE), and an output that generates an inverted enable signal (EN); a first transistor, including a first terminal for receiving E, a second terminal for receiving SE, and a third terminal; a second transistor, including a first terminal, a second terminal for receiving EN, and a third terminal connected to the first terminal of the first transistor; a third transistor, including a first terminal connected to the third terminal of the first transistor, a second terminal for receiving a clock signal (CK), and a third terminal; a fourth transistor, including a first terminal connected to the first terminal of the second transistor, a second terminal for receiving an enabled clock signal (ECKN), and a third terminal connected to the third terminal of the third transistor; a fifth transistor, including a first terminal connected to a power supply voltage (VDD), a second terminal connected to the output of the logic gate, and a third terminal connected to the third terminal of the first transistor; a sixth transistor, including a first terminal connected to the first terminal of the second transistor, a second terminal connected to VDD, and a third terminal; a seventh transistor, including a first terminal, a second terminal connected to the third terminal of the third transistor, and a third terminal connected to the third terminal of the sixth transistor; an eighth transistor, including a first terminal connected to VDD, a second terminal for receiving ECKN, and a third terminal connected to the second terminal of the seventh transistor; a ninth transistor, including a first terminal connected to VDD, a second terminal connected to the second terminal of the seventh transistor, and a third terminal connected to the first terminal of the seventh transistor; a tenth transistor, including a first terminal connected to VDD, a second terminal for receiving CK, and a third terminal connected to the first terminal of the seventh transistor; an eleventh transistor, including a first terminal connected to the third terminal of the seventh transistor, a second terminal for receiving CK, and a third terminal connected to a ground; and an inverter, including an input connected to the third terminal of the tenth transistor, and an output for generating an enabled clock signal (ECK).
15. The integrated clock gating cell of claim 14 , wherein the logic gate is a NOR gate.
16. The integrated clock gating cell of claim 14 , wherein the first transistor, the third transistor, the fifth transistor, the eighth transistor, the ninth transistor, and the tenth transistor are each a p-channel metal oxide semiconductor (PMOS) transistor.
17. The integrated clock gating cell of claim 14 , wherein the second transistor, the fourth transistor, the sixth transistor, the seventh transistor, and the eleventh transistor are each an n-channel metal oxide semiconductor (NMOS) transistor.
18. The integrated clock gating cell of claim 16 , wherein the first and third terminal of each PMOS transistor is either a source terminal or a drain terminal, and wherein the second terminal of each transistor is a gate terminal.
19. The integrated clock gating cell of claim 17 , wherein the first and third terminal of each NMOS transistor is either a source terminal or a drain terminal, and wherein the second terminal of each transistor is a gate terminal.
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February 7, 2017
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