Legal claims defining the scope of protection, as filed with the USPTO.
1. An interconnect element in a network-processing system on chip, comprising: a plurality of primary input ports and a plurality of primary output ports configured to connect with other interconnect elements; a plurality of PE ports configured to connect with a plurality of local processing engines (PEs); a routing kernel configured to route a plurality of incoming packets; a pool of shared memory tiles configured to form one or more lookup tables utilized by its local PEs, wherein the lookup tables include front and back interconnection fabrics of the pool of memory tiles configured to connect the memory tiles to input and output interfaces of the lookup tables, respectively.
2. The interconnect element of claim 1 , wherein the primary input ports and primary output ports are configured to directly connect with other interconnect elements for building a bigger on-chip network to support a larger number of processing engines.
3. The interconnect element of claim 1 , wherein each of the local PE ports is configured to connect to one local PE of the interconnect element.
4. The interconnect element of claim 1 , wherein the PEs in an entire system communicate with each other indirectly through a network built from an array of interconnect elements.
5. The interconnect element of claim 1 , wherein each of the local PEs has one or more PE virtual addresses, which are used by the interconnect element for transferring the incoming packets among the PEs.
6. The interconnect element of claim 5 , wherein each of the PE virtual addresses is used to locate the PE that owns the PE virtual address and also to decide the local lookup table inside the interconnect element for performing the lookup operations before the incoming packets are sent to that PE.
7. The interconnect element of claim 1 , wherein the pool of memory tiles are either static random-access memory (SRAM) or ternary content-addressable memory (TCAM) modules.
8. The interconnect element of claim 1 , wherein the pool of memory tiles allocated for each lookup table is user-configurable and follows rules of: 1) the number of the memory tiles per table is a power of two; 2) the memory tiles for each lookup table are at consecutive locations; 3) there is no overlap between any two lookup tables; 4) the number of the lookup tables is no more than hardware-supported maximum number of lookup tables, which is equal to the number of the memory tiles.
9. The interconnect element of claim 1 , wherein each of the lookup tables is configured to be dedicated to one local PE or to be shared by multiple local PEs; and one PE accesses one or multiple lookup tables at run-time.
10. The interconnect element of claim 1 , wherein each of the interconnect fabrics is a crossbar or a configurable butterfly network.
11. The interconnect element of claim 1 , wherein the router kernel includes: routing tables for determining one of the output ports and one of the lookup tables for the incoming packets; arbiters for resolving conflicts in cases there are multiple incoming packets from different input ports to be forwarded to the same output port or to access the same lookup table; a first and a second crossbar for transferring the incoming packets accordingly to outcomes of the arbiters.
12. The interconnect element of claim 11 , wherein the routing tables are programmable, and are dedicated per input port or shared by all input ports if they have the same content.
13. The interconnect element of claim 12 , wherein each of the routing tables uses a destination PE virtual address field in each input packet as an index for determining the output port and lookup table for the input packet.
14. The interconnect element of claim 11 , wherein the arbiters act in a round-robin fashion to achieve fairness among all of the input packets.
15. The interconnect element of claim 11 , wherein the first crossbar in configured to connect input ports to primary output ports and input interfaces of the lookup tables, and wherein the second crossbar is configured to connect output interfaces of lookup tables to output ports going to local processing engines.
16. A method for configuring an interconnect element in a network-processing system on chip, comprising: determining number of active lookup tables needed for a plurality of local processing engines (PEs) attached to the interconnect element; partitioning a pool of memory tiles for each of the lookup tables including number of memory tiles per table and locations of the memory tiles; programming contents of the active lookup tables based on structure and/or type of the memory tiles; mapping PE virtual addresses of the local PEs to the partitioned lookup tables; programming a plurality of routing tables at input ports of the interconnect element, wherein the routing tables are configured to allow the incoming packets to the interconnect element to determine their output ports and the local lookup tables for performing lookups if the incoming packets go to the local PEs.
17. The method of claim 16 , wherein the PE virtual addresses are used by the interconnect element for transferring the incoming packets among the PEs.
18. The method of claim 16 , wherein each of the PE virtual addresses is used to locate the PE that owns the PE virtual address and also to decide one of the local lookup tables inside the interconnect element for performing the lookup operations before the incoming packets are sent to that PE.
19. The method of claim 16 , wherein the pool of memory tiles are either static random-access memory (SRAM) or ternary content-addressable memory (TCAM) modules.
20. The method of claim 16 , further comprising: partitioning the pool of memory tiles for each of the lookup tables following all the rules of: 1) the number of the memory tiles per table is a power of two; 2) the memory tiles for each lookup table are at consecutive locations; 3) there is no overlap between any two lookup tables; 4) the number of the lookup tables is no more than hardware-supported maximum number of lookup tables, which is equal to the number of the memory tiles.
21. The method of claim 16 , further comprising: sharing each of the lookup tables by multiple local PEs.
22. The method of claim 16 , further comprising: configuring one PE to access multiple lookup tables at run-time.
23. The method of claim 16 , further comprising: partitioning the lookup tables are partitioned by configuring front and back interconnection fabrics of the pool of memory tiles, wherein the front and back interconnection fabrics connect the memory tiles to input and output interfaces of the lookup tables.
24. The method of claim 23 , wherein each of the interconnect fabrics is a crossbar or a configurable butterfly network.
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February 14, 2017
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