Carry-Skip One-Bit Full Adder and FPGA Device

1. A carry-skip one-bit full adder, wherein the full adder comprises: a first multiplexer, a second multiplexer, and an adder; the first multiplexer comprises a first addend input end and a first constant input end, the first constant input end being configured to input a first constant to the first multiplexer; and the second multiplexer comprises a second addend input end and a second constant input end, the second constant input end being configured to input a second constant to the second multiplexer; and when the first addend input end is not used for input of a first addend, and/or when the second addend input end is not used for input of a second addend, the first multiplexer selects to output the first constant input by the first constant input end, and the second multiplexer selects to output the second constant input by the second constant input end, so that a carry output end of the adder generates a determined additive carry-out signal according to the first constant and the second constant.

2. The full adder according to claim 1 , wherein when either of the first constant and the second constant is a digital high level and the other is a digital low level, the additive carry-out signal is an additive carry-in signal input by a carry input end of the adder.

3. The full adder according to claim 2 , wherein, when in the current full adder, either of the first constant and the second constant is a digital high level and the other is a digital low level, the current full adder transmits the input additive carry-in signal to a carry input end of a next full adder cascaded with the current full adder, so that the input additive carry-in signal is used as an additive carry-in signal of the next full adder.

4. The full adder according to claim 1 , when the first constant and the second constant are both digital high levels, the additive carry-out signal is a digital high level.

5. The full adder according to claim 4 , wherein, when in the current full adder, the first constant and the second constant are both digital high levels, the current full adder is configured to provide a digital high-level additive carry-in signal for a next full adder cascaded with the current full adder; and when in the current full adder, the first constant and the second constant are both digital low levels, the current full adder is configured to provide a digital low-level additive carry-in signal for a next full adder cascaded with the current full adder.

6. The full adder according to claim 1 , when the first constant and the second constant are both digital low levels, the additive carry-out signal is a digital low level.

7. The full adder according to claim 6 , wherein, when in the current full adder, the first constant and the second constant are both digital high levels, the current full adder is configured to provide a digital high-level additive carry-in signal for a next full adder cascaded with the current full adder; and when in the current full adder, the first constant and the second constant are both digital low levels, the current full adder is configured to provide a digital low-level additive carry-in signal for a next full adder cascaded with the current full adder.

8. The full adder according to claim 1 , wherein the second multiplexer further comprises an inversion logic output control end; when the inversion logic output control end inputs a digital high-level signal, the second multiplexer outputs the second addend or the second constant; and when the inversion logic output control end inputs a digital low-level signal, the second multiplexer outputs an inverted signal of the second addend or an inverted signal of the second constant.

9. The full adder according to claim 1 , wherein the second multiplexer further comprises an inversion logic output control end; when the inversion logic output control end inputs a digital low-level signal, the second multiplexer outputs the second addend or the second constant; and when the inversion logic output control end inputs a digital high-level signal, the second multiplexer outputs an inverted signal of the second addend or an inverted signal of the second constant.

10. A field programmable gate array (FPGA) device, wherein the FPGA device comprises multiple logic elements (LEs), each element comprises a logic parcel (LP), and each LP comprises two full adders according to claim 1 ; and a carry input end of an adder of the first full adder in a current LP is connected to a carry output end of an adder of the second full adder in a previous LP; a carry output end of an adder of the second full adder in the current LP is connected to a carry input end of an adder of the first full adder in a next LP; wherein, in each LP, a carry output end of an adder of the first full adder is connected to a carry input end of an adder of the second full adder.