Method and Apparatus for Validating a System-On-Chip Based on a Silicon Fingerprint and a Unique Response Code

1. A system-on-chip comprising: a plurality of circuit instances having respectively a first plurality of nodes, wherein the plurality of circuit instances are designed to provide nominally a same value at each of the first plurality of nodes; a selector module configured to generate a first selection signal; a circuit instance module configured to (i) monitor a plurality of states of the first plurality of nodes, and (ii) based on the first selection signal, select (a) two or more of the plurality of states of the first plurality of nodes, or (b) two or more parameter values generated based on the two or more of the plurality of states of the first plurality of nodes; a first comparing module configured to compare (i) the two or more of the states of the first plurality of nodes, or (ii) the two or more parameter values, and based on the comparison, output a first bit of (i) a silicon fingerprint of the system-on-chip, or (ii) a unique response code of the system-on-chip; a second comparing module configured to generate a comparison signal based on a comparison between the silicon fingerprint and the unique response code; a mode module configured to operate in a secure mode based on the comparison signal; and a countermeasure module configured to, based on the comparison signal, perform a countermeasure.

2. The system-on-chip of claim 1 , wherein: the selector module is configured to generate a plurality of selection signals; the plurality of selection signals includes the first selection signal and a second selection signal; the circuit instance module is configured to during generation of the first bit of the silicon fingerprint or the unique response code and based on the first selection signal, select a first state of a first node and a state of a second node, and during generation of a second bit of the silicon fingerprint or the unique response code and based on the second selection signal, select a second state of the first node and a state of a third node; the first plurality of nodes comprise the first node, the second node and the third node; and the first comparing module is configured to (i) compare the first state of the first node to the state of the second node to generate the first bit, and (ii) compare the second state of the first node to the state of the third node to generate the second bit.

3. The system-on-chip of claim 2 , wherein the first state of the first node, the second state of the first node, the state of the second node, and the state of the third node are voltages of resistance capacitance circuits.

4. The system-on-chip of claim 1 , wherein: the selector module is configured to generate a plurality of selection signals; the plurality of selection signals includes the first selection signal and a second selection signal; the circuit instance module is configured to during generation of the first bit of the silicon fingerprint or the unique response code and based on the first selection signal, (i) generate a first parameter value based on a first state of a first node, and (ii) generate a second parameter value based on a state of a second node, and during generation of a second bit of the silicon fingerprint or the unique response code and based on the second selection signal, (i) generate a third parameter value based on a second state of the first node, and (ii) generate a fourth parameter value based on a state of a third node; the first plurality of nodes comprise the first node, the second node and the third node; and the first comparing module is configured to (i) compare the first parameter value and the second parameter value to generate the first bit, and (ii) compare the third parameter value and the fourth parameter value to generate the second bit.

5. The system-on-chip of claim 4 , wherein the first parameter value, the second parameter value, the third parameter value, and the fourth parameter value are frequencies.

6. The system-on-chip of claim 1 , further comprising a control module configured to, prior to the circuit instance module monitoring the first plurality of nodes, select the first plurality of nodes from a second plurality of nodes in the system-on-chip.

7. The system-on-chip of claim 1 , further comprising: a memory; the first comparing module is configured to, during a first iteration, (i) perform a first comparison (a) to compare the two or more of the plurality of states of the first plurality of nodes, or (b) the two or more parameter values, and (ii) based on the first comparison, storing the first bit of the silicon fingerprint of the system-on-chip in the memory; and the first comparing module is configured to, during a second iteration, (i) perform a second comparison between (a) updated versions of the two or more of the plurality of states of the first plurality of nodes, or (b) updated versions of the two or more parameter values, and (ii) based on the second comparison, storing a second bit of the unique response code of the system-on-chip in the memory.

8. The system-on-chip of claim 1 , wherein the first comparing module is configured to iteratively update the unique response code based on (a) corresponding updated versions of the two or more of the states of the first plurality of nodes, or (b) corresponding updated versions of the two or more parameter values.

9. The system-on-chip of claim 1 , wherein the first comparing module is configured to (i) generate the silicon fingerprint based on (a) the two or more of the states of the first plurality of nodes, or (b) the two or more parameter values, and (ii) generate the unique response code based on (a) updated versions of the two or more of the states of the first plurality of nodes, or (b) updated versions of the two or more parameter values.

10. The system-on-chip of claim 1 wherein: each of the first plurality of nodes of the plurality of circuit instances is connected to the circuit instance module; and the state of each of the first plurality of nodes is independent of the states of the other ones of the first plurality of nodes.

11. The system-on-chip of claim 1 , wherein: the circuit instance module comprises a multiplexer; the multiplexer is configured to (i) receive outputs of the circuit instances, and (ii) output two or more of the outputs based on the selection signal; the two or more outputs have the two or more states of the first plurality of nodes; and the first comparing module is configured to compare the two or more outputs.

12. The system-on-chip of claim 1 , wherein each of the plurality of states is a state of a respective one of the first plurality of nodes.

13. A method of operating a system-on-chip, wherein the system-on-chip includes a plurality of circuit instances having respectively a first plurality of nodes, and wherein the plurality of circuit instances are designed to provide nominally a same value at each of the plurality of nodes, the method comprising: generate a first selection signal; monitoring a plurality of states of the first plurality of nodes; based on the first selection signal, selecting (a) two or more of the plurality of states of the first plurality of nodes, or (b) two or more parameter values generated based on the two or more of the plurality of states of the first plurality of nodes; comparing (i) the two or more of the states of the first plurality of nodes, or (ii) the two or more parameter values; based on the comparison, generating a first bit of (i) a silicon fingerprint of the system-on-chip, or (ii) a unique response code of the system-on-chip; generating a comparison signal based on a comparison between the silicon fingerprint and the unique response code; operating in a secure mode based on the comparison signal; and based on the comparison signal, performing a countermeasure.

14. The method of claim 13 , further comprising: generating a plurality of selection signals, wherein the plurality of selection signals includes the first selection signal and a second selection signal; during generation of the first bit of the silicon fingerprint or the unique response code and based on the first selection signal, selecting a first state of a first node and a state of a second node, and during generation of a second bit of the silicon fingerprint or the unique response code and based on the second selection signal, selecting a second state of the first node and a state of a third node, wherein the first plurality of nodes comprise the first node, the second node and the third node; comparing the first state of the first node to the state of the second node to generate the first bit; and comparing the second state of the first node to the state of the third node to generate the second bit.

15. The method of claim 14 , wherein the first state of the first node, the second state of the first node, the state of the second node, and the state of the third node are voltages of resistance capacitance circuits.

16. The method of claim 13 , further comprising: generating a plurality of selection signals, wherein the plurality of selection signals includes the first selection signal and a second selection signal; during generation of the first bit of the silicon fingerprint or the unique response code and based on the first selection signal, (i) generating a first parameter value based on a first state of a first node, and (ii) generating a second parameter value based on a state of a second node; during generation of a second bit of the silicon fingerprint or the unique response code and based on the second selection signal, (i) generating a third parameter value based on a second state of the first node, and (ii) generating a fourth parameter value based on a state of a third node, wherein the first plurality of nodes comprise the first node, the second node and the third node; comparing the first parameter value and the second parameter value to generate the first bit; and comparing the third parameter value and the fourth parameter value to generate the second bit.

17. The method of claim 16 , wherein the first parameter value, the second parameter value, the third parameter value, and the fourth parameter value are frequencies.

18. The method of claim 13 , further comprising, prior to the monitoring of the first plurality of nodes, selecting the first plurality of nodes from a second plurality of nodes in the system-on-chip.

19. The method of claim 13 , further comprising: during a first iteration, (i) performing a first comparison (a) to compare the two or more of the plurality of states of the first plurality of nodes, or (b) the two or more parameter values, and (ii) based on the first comparison, storing the first bit of the silicon fingerprint of the system-on-chip in a memory; and during a second iteration, (i) performing a second comparison between (a) updated versions of the two or more of the plurality of states of the first plurality of nodes, or (b) updated versions of the two or more parameter values, and (ii) based on the second comparison, storing a second bit of the unique response code of the system-on-chip in the memory.

20. The method of claim 13 , further comprising iteratively updating the unique response code based on (a) corresponding updated versions of the two or more of the states of the first plurality of nodes, or (b) corresponding updated versions of the two or more parameter values.

21. The method of claim 13 , further comprising: generating the silicon fingerprint based on (a) the two or more of the states of the first plurality of nodes, or (b) the two or more parameter values; and generating the unique response code based on (a) updated versions of the two or more of the states of the first plurality of nodes, or (b) updated versions of the two or more parameter values.