Legal claims defining the scope of protection, as filed with the USPTO.
1. A display driver, comprising: a voltage source having a plurality of voltage outputs distributed in magnitude, a selection circuit having a first output of a first voltage and a second output of a second voltage, the first and second voltages being two of the voltages output by the voltage source and selected in response to a first portion of display data received by the selection circuit; and an output selector circuit, receiving the first and second voltages as inputs, and having a number of x voltage outputs where x is an integer greater or equal to two, the x voltage outputs being a number of y first voltages and a number of x-y second voltages, where y is an integer greater or equal to zero determined in response to a second portion of display data received by output selector circuit; and an amplifier including x first circuits, each first circuit having an input of a corresponding one of the x voltage outputs of the output selector circuit, each first circuit comprising: a first nMOS transistor, a second nMOS transistor and a bias circuit, the first nMOS transistor having a gate connected to the input of the first circuit of the corresponding one of the x voltage outputs of the output selector, and having a source-channel-drain current path serially connected to the bias circuit, the second nMOS transistor having a source-channel-drain current path serially connected to the bias circuit; wherein gates of the second nMOS transistors of the x first circuits are connected in common, a first node having connections to drains of the first nMOS transistors; and a second node having connections to drains of the second nMOS transistors of the first circuits; and a second circuit responsive to a voltage on the first node to output a voltage to drive a display panel.
2. The device of claim 1 , where the second portion of display data may select x to be any integer from zero to x.
3. The device of claim 1 , further comprising first and second pMOS transistors, gates of the first and second pMOS transistors and the source of the second pMOS transistor sharing a common node, the drain of the first pMOS transistor connected to the first node and the drain of the second pMOS transistor connected to the second node.
4. The device of claim 3 , wherein the sources of the first and second pMOS transistors are connected to a supply voltage.
5. The display driver of claim 1 , wherein each bias circuit is directly connected to ground.
6. The display driver of claim 1 , wherein the source of each first nMOS transistor is directly connected to the corresponding bias circuit.
7. The display driver of claim 1 , wherein each bias circuit is a current source.
8. The display driver of claim 1 , wherein the display driver is a source driver IC.
9. A method of driving a display panel, receiving image data representing a pixel gray scale; generating a plurality of gray voltages having different magnitudes; selecting a first voltage and a second voltage of the plurality of gray voltages in response to a first portion of the image data; in response to a second portion of the image data, outputting x output voltages where x is an integer greater or equal to two, the x output voltages being y first voltages and x-y second voltages, where y is an integer greater or equal to zero, interpolating the x output voltages by providing each of the x output voltages to a corresponding one of x first circuits, each first circuit comprising a first nMOS transistor, a second nMOS transistor and a bias circuit, the first nMOS transistor having a gate connected to the input of the first circuit, and having a source-channel-drain current path connected to the bias circuit, the second nMOS transistor having a source-channel-drain current path connected to the bias circuit; and providing an interpolated voltage on a node connected to each first circuit; and driving a display panel with a voltage having a magnitude correlating to the interpolated voltage on the node.
10. The method of claim 9 , wherein gates of the second nMOS transistors of the x first circuits are connected in common, wherein drains of the second nMOS transistors of the x first circuits are connected in common, and wherein drains of the first nMOS transistors of the x first circuits are connected in common at the node.
11. The method of claim 9 , wherein the selecting of the first voltage and the second voltage of the plurality of gray voltages is performed by a gamma decoder.
12. A method of driving a display panel, comprising: receiving image data for a pixel of a display; selecting first and second voltages of a plurality of sequentially increasing voltages, the selection being responsive to the image data, the first voltage and the second voltage being different from each other; generating a third voltage corresponding to an average of x first voltages and y second voltages, x and y being integers equal to or greater than one, the third voltage generated by applying a voltage corresponding to the first voltage to gates of x nMOS transistors, and by applying a voltage corresponding to the second voltage to gates of y nMOS transistors, each of the x nMOS transistors and y nMOS transistors connected to a respective separate bias circuit that is not connected to any of the others of the x nMOS transistors and y nMOS transistors; determining x and y in response to the image data; providing a fourth voltage corresponding to the third voltage to a display panel to drive the pixel.
13. The method of claim 12 , wherein the sum of x and y equals a constant for different image data.
14. The method of claim 13 , wherein the image data has sufficient information to select any integer between zero and the constant for x and for y in the determining step.
15. The method of claim 12 , wherein each bias circuit is connected directly to ground.
16. The method of claim 12 , wherein each bias circuit is a current source.
17. The method of claim 12 , wherein the selecting of the first and second voltages is performed by a gamma decoder.
18. The method of claim 12 , wherein each of the x nMOS transistors and y nMOS transistors include a drain, the drains of the x nMOS transistors and y nMOS transistors being connected together.
19. A display system comprising: a display panel comprising a plurality of pixels; a plurality of source conducting lines to transmit a gray voltage corresponding to a brightness value to drive a pixel; a plurality of source voltage drivers, each connected to a corresponding source conducting lines, each comprising: a voltage source having a plurality of voltage outputs distributed in magnitude, a selection circuit having a first output of a first voltage and a second output of a second voltage, the first and second voltages being two of the voltages output by the voltage source and selected in response to a first portion of display data received by the selection circuit; and an output selector circuit, receiving the first and second voltages as inputs, and having a number of x voltage outputs where x is an integer greater or equal to two, the x voltage outputs being a number of y first voltages and a number of x-y second voltages, where y is an integer greater or equal to zero determined in response to a second portion of display data received by output selector circuit; and an amplifier including x first circuits, each first circuit having an input of a corresponding one of the x voltage outputs of the output selector circuit, each first circuit comprising: a first nMOS transistor, a second nMOS transistor and a bias circuit, the first nMOS transistor having a gate connected to the input of the first circuit of the corresponding one of the x voltage outputs of the output selector, and having a source-channel-drain current path serially connected to the bias circuit, the second nMOS transistor having a source-channel-drain current path serially connected to the bias circuit; a conductor to connect gates of the second nMOS transistors in common; a first node having connections to drains of the first nMOS transistors; and a second node having connections to drains of the second nMOS transistors of the first circuits; and a second circuit responsive to a voltage on the first node to output a voltage on the corresponding source conducting lines to drive the display panel.
20. The system of claim 19 , where the second portion of display data may select x to be any integer from zero to x.
21. The system of claim 19 , further comprising first and second pMOS transistors, gates of the first and second pMOS transistors and the source of the second pMOS transistor sharing a common node, the drain of the first pMOS transistor connected to the first node and the drain of the second pMOS transistor connected to the second node.
22. The system of claim 21 , wherein the sources of the first and second pMOS transistors are connected to a supply voltage.
23. The system of claim 19 , wherein each bias circuit is directly connected to ground.
24. The system of claim 19 , wherein the source of each first nMOS transistor is directly connected to the corresponding bias circuit.
25. The system of claim 19 , wherein each bias circuit is a current source.
26. The system of claim 19 , further comprising a gamma decoder, wherein the selection circuit is an element of the gamma decoder.
27. A display comprising: a display panel comprising a plurality of pixels; a plurality of conducting lines to transmit a gray voltage image signal corresponding to a brightness value to drive a pixel; a plurality of display drivers, each connected to a corresponding conducting line, each display driver comprising a gamma decoder to generate at least four analog gray voltages and an amplifier to receive the at least four analog gray voltages generated by the gamma decoder and to output an analog output voltage corresponding to the gray voltage image signal transmitted by the corresponding conducting line, each gamma decoder comprising: a voltage source having a plurality of voltage outputs distributed in magnitude, a selection circuit having a first output of a first voltage and a second output of a second voltage, the first and second voltages being two of the voltages output by the voltage source and selected in response to a first portion of display data received by the selection circuit; and an output selector circuit, receiving the first and second voltages as inputs, and having at least four voltage outputs including a number of y first voltages and a number of four minus y second voltages, where y is an integer greater or equal to zero determined in response to a second portion of display data received by output selector circuit; each amplifier comprising: at least four first circuits, each first circuit having an input of a corresponding one of the four voltage outputs of the output selector circuit, each first circuit comprising: a first nMOS transistor, a second nMOS transistor and a bias circuit, the first nMOS transistor having a gate connected to the input of the first circuit of the corresponding one of the four voltage outputs of the output selector, and having a source-channel-drain current path connected to the bias circuit, the second nMOS transistor having a source-channel-drain current path connected to the bias circuit; a conductor to connect gates of the second nMOS transistors in common; a first node having connections to drains of the first nMOS transistors; and a second node having connections to drains of the second nMOS transistors of the first circuits; and a second circuit responsive to a voltage on the first node to output a voltage on the corresponding conducting lines to drive the display panel.
28. The display of claim 27 , further comprising: gate lines and source lines arranged on the display panel, wherein the plurality of conducting lines are the source lines and the each of the display drivers is a source driver.
29. The display of claim 28 , wherein the source lines connect to transistors which connect to pixel electrodes.
30. The display of claim 29 , wherein the display is a liquid crystal display comprising a liquid crystal layer disposed between an upper plate and a lower plate, wherein the transistors are thin film transistors and connect to electrodes to re-arrange liquid crystal polymers in the liquid crystal layer to cause a gray level corresponding to the voltage provided on the corresponding source conducting line.
31. The display of claim 28 , wherein the source driver is located adjacent to the display panel.
32. The display of claim 28 , wherein the source driver is located on the display panel.
33. The display of claim 32 , wherein the source driver is located in a chip.
34. The display of claim 28 , wherein the display panel is a panel of one of the group consisting of: thin film transistor liquid crystal display, electro luminance display, super twisted nematic liquid crystal display and plasma display panel.
35. A display driver comprising: a gamma decoder to generate at least four analog gray voltages; and an amplifier to receive the at least four analog gray voltages generated by the gamma decoder and to output an image signal voltage; wherein each gamma decoder comprises: a voltage source having a plurality of voltage outputs distributed in magnitude, a selection circuit having a first output of a first voltage and a second output of a second voltage, the first and second voltages being two of the voltages output by the voltage source and selected in response to a first portion of display data received by the selection circuit; and an output selector circuit, receiving the first and second voltages as inputs, and having at least four voltage outputs including a number of y first voltages and a number of four minus y second voltages, where y is an integer greater or equal to zero determined in response to a second portion of display data received by output selector circuit; wherein each amplifier comprises: at least four first circuits, each first circuit having an input of a corresponding one of the at least four voltage outputs of the output selector circuit, each first circuit comprising: a first nMOS transistor, a second nMOS transistor and a bias circuit, the first nMOS transistor having a gate connected to the input of the first circuit of the corresponding one of the four voltage outputs of the output selector, and having a source-channel-drain current path connected to the bias circuit, the second nMOS transistor having a source-channel-drain current path connected to the bias circuit; a conductor to connect gates of the second nMOS transistors in common; a first node having connections to drains of the first nMOS transistors; and a second node having connections to drains of the second nMOS transistors of the first circuits; and a second circuit responsive to a voltage on the first node to output the image signal voltage.
36. The display driver of claim 35 , wherein the display driver is a source driver located in a chip.
Unknown
March 21, 2017
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