Traffic Control on an On-Chip Network

1. A method of controlling traffic on an on-chip network, the method comprising: injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network; receiving the packet at a second node coupled to the on-chip network; determining that the received packet is to be deflected and not buffered by the second node; modifying a first bit in the received packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change and a second bit different than the first bit in the received packet to indicate that the received packet was deflected; returning the packet with the first and second bits modified to the first node by the second node; and changing the first rate by the first node in response to detecting that the first and second bits in the packet were modified.

2. The method of claim 1 , wherein determining by the second node that a rate at which packets are injected into the on-chip network should change comprises determining that the first rate should be reduced.

3. The method of claim 2 , wherein determining that the first rate should be reduced comprises determining that the second node lacks resources to handle the packet at the time the second node receives the packet.

4. The method of claim 2 , wherein determining that the first rate should be reduced comprises determining that a number of packets deflected by the second node exceeds a threshold number.

5. The method of claim 1 , wherein the second node is a destination node for the packet.

6. The method of claim 1 , wherein the second node is an intermediate node to forward the packet to a destination node.

7. The method of claim 1 , wherein returning the packet to the first node comprises transmitting the packet to the first node via a pre-defined route.

8. The method of claim 7 , wherein the pre-defined route is a route the packet took from the first node to the second node.

9. The method of claim 1 , wherein returning the packet to the first node comprises transmitting the packet to the first node via a random route.

10. The method of claim 1 , wherein the on-chip network is a buffered network.

11. A non-transitory computer-readable storage medium having content stored thereon, which when executed causes one or more processors having nodes organized as an on-chip buffered network to: inject a packet at a first rate into the on-chip network by a first node coupled to the on-chip network; receive the packet at a second node coupled to the on-chip network; determine that the received packet is to be deflected and not buffered by the second node; modify a first bit in the received packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change and a second bit different than the first bit in the received packet to indicate that the received packet was deflected; return the packet with the first and second bits modified to the first node by the second node; and change the first rate by the first node in response to detecting that the first and second bits in the packet were modified.