Methods and Systems for Implementing Redundancy in Memory Controllers

1. A method for introducing redundancy in a memory controller, the method comprising: providing a plurality of data memory elements, each data memory element being associated with a corresponding non-volatile storage element, the plurality of data memory elements including a parity data memory element, and a control memory element comprising a plurality of entries, each entry corresponding to a data memory element from the plurality of data memory elements; initializing, by the memory controller, the plurality of entries of the control memory element to a first value; storing, by the memory controller, a received first data block from a host computer to the first data memory element and, if an entry in the control memory element corresponding to the parity data memory element has the first value, to the parity data memory element; changing, by the memory controller, to a second value an entry in the control memory element corresponding to the first data memory element and the entry in the control memory element corresponding to the parity data memory element; storing, by the memory controller, a received second data block from the host computer to a second data memory element; and storing, by the memory controller, to the parity data memory element a result of a logical operation between a value in the second data block and the value in the parity data memory element, if the entry in the control memory element corresponding to the parity data memory element has the second value.

2. The method of claim 1 , further comprising: transferring, by the memory controller, the stored data from the data memory elements to their corresponding non-volatile storage elements; and initializing, by the memory controller, the data memory elements to a logical zero, after transferring the stored data from the data memory elements to the non-volatile storage elements.

3. The method of claim 1 , wherein the first value corresponds to an invalid state and the second value corresponds to a valid state.

4. The method of claim 1 , wherein the logical operation is an exclusive OR logical operation.

5. The method of claim 4 , wherein the result of the exclusive OR logical operation is stored into the parity data memory element incrementally.

6. The method of claim 4 , wherein the value stored in a first data memory element can be restored from values of the data memory elements in a valid state and the value of the parity data memory element.

7. The method of claim 1 , wherein each corresponding non-volatile storage element is located in an independent media unit.

8. The method of claim 1 , further comprising: transferring, by the memory controller, the stored data from the data memory elements to their corresponding non-volatile storage elements; and initializing, by the memory controller, at least one entry of the plurality of entries of the control memory element to logical zero, after transferring the stored data from the data memory elements to the non-volatile storage elements.

9. A memory controller comprising: a plurality of data memory elements, each data memory element being associated with a corresponding non-volatile storage element, the plurality of data memory elements including a parity data memory element; a control memory element comprising a plurality of entries, each entry corresponding to a data memory element from the plurality of data memory elements; and a controller module configured to: initialize the plurality of entries of the control memory element to a first value; store a received first data block from a host computer to the first data memory element and, if an entry in the control memory element corresponding to the parity data memory element has the first value, to the parity data memory element; change to a second value an entry in the control memory element corresponding to the first data memory element and the entry in the control memory element corresponding to the parity data memory element; store a received second data block from the host computer to a second data memory element; and store to the parity data memory element a result of a logical operation between a value in the second data block and the value in the parity data memory element, if the entry in the control memory element corresponding to the parity data memory element has the second value.

10. The memory controller of claim 9 , wherein the controller module is further configured to: transfer the stored data from the data memory elements to their corresponding non-volatile storage elements; and initialize the data memory elements to a logical zero, after transferring the stored data from the data memory elements to the first non-volatile storage elements.

11. The memory controller of claim 9 , wherein the first value corresponds to an invalid state and the second value corresponds to a valid state.

12. The memory controller of claim 9 , wherein the logical operation is an exclusive OR logical operation.

13. The memory controller of claim 12 , wherein the result of the exclusive OR logical operation is stored into the parity data memory element incrementally.

14. The memory controller of claim 12 , wherein a value stored in a first data memory element can be restored from the values of the data memory elements in a valid state and a value of the parity data memory element.

15. The memory controller of claim 9 , wherein each corresponding non-volatile storage element is located in an independent media unit.

16. The memory controller of claim 9 , wherein the controller module is further configured to: transfer the stored data from the data memory elements to their corresponding non-volatile storage elements; and initialize at least one entry of the plurality of entries of the control memory element to logical zero, after transferring the stored data from the data memory elements to the non-volatile storage elements.