System and Method for Automatically Enforcing Schematic Layout Strategy Selectively Applied to Schematic Objects

1. A system for automatically enforcing a schematic layout strategy applied to a group of schematically represented circuit objects of an electronic circuit design, comprising: a circuit editing tool accessing a graphic database to electronically render schematic representations of the circuit objects responsive to user input, said circuit editing tool having a graphic user interface and a display for graphically displaying the schematic representations on one or more graphic pages; a layout object acquisition unit coupled to said circuit editing tool, said layout object acquisition unit being actuated responsive to user input to selectively apply a predetermined layout strategy to at least one group of circuit objects selected from a pre-existing portion of a schematic representation of the electronic circuit design to reconfigure said group of circuit objects into a layout object corresponding to the predetermined layout strategy, said group of circuit objects including circuit objects of differing object types, said predetermined layout strategy including a defining set of expected circuit objects and a defining set of placement and interconnection routing schemes for the schematic representation of the grouped circuit objects one relative to the other, said placement scheme placing at least one circuit object relative to another circuit object of different object type, said predetermined layout strategy predefined and previously stored as one of a plurality of layout strategies representing a plurality of defining sets of expected circuit objects; and, a layout object management unit coupled to said layout object acquisition unit and said circuit editing tool, said layout object management unit adaptively reconfiguring said layout object in accordance with the layout strategy thereof responsive to an editing operation being imposed on at least one circuit object within said layout object, wherein the electronic circuit design represents an electronic circuit to be produced.

2. The system as recited in claim 1 , wherein said placement scheme of said predetermined layout strategy includes relative margin and spacing attributes to be preserved between at least neighboring pairs of said circuit objects when schematically represented within said layout object.

3. The system as recited in claim 2 , wherein said interconnect routing scheme of said predetermined layout strategy defines at least one of: a bypass capacitor rail sub-circuit, a Thevenin termination sub-circuit; a pull-up voltage coupling sub-circuit; a pull-down voltage coupling sub-circuit; and, a filter sub-circuit.

4. The system as recited in claim 3 , wherein said layout object management unit executes at least one of the following adaptive actions within a schematic representation of the electronic circuit design: move said layout object; rotate said layout object; re-size said layout object; re-format the margin or spacing attributes of said layout object; merge a plurality of said layout objects; re-arrange the circuit objects of said layout object; reconstitute the circuit objects of said layout object; and, re-connect the reconstituted circuit objects of said layout object.

5. The system as recited in claim 3 , wherein said layout object acquisition unit is selectively executable to merge a plurality of said layout objects within a schematic representation of the electronic circuit design.

6. A system for automatically enforcing a schematic layout strategy applied to a group of schematically represented circuit objects of an electronic circuit design, comprising: a circuit editing tool accessing a graphic database to electronically render schematic representations of the circuit objects responsive to user input, said circuit editing tool having a graphic user interface and a display for graphically displaying the schematic representations on one or more graphic pages; a layout object acquisition unit coupled to said circuit editing tool, said layout object acquisition unit being actuated responsive to user input to selectively apply a predetermined layout strategy to at least one group of circuit objects selected from a pre-existing portion of a schematic representation of the electronic circuit design to generate a layout object corresponding to the predetermined layout strategy, said group of circuit objects including circuit objects of differing object types, said predetermined layout strategy including a defining set of expected circuit objects and a defining set of placement and interconnection routing schemes for the schematic representation of the grouped circuit objects one relative to the other, said placement scheme placing at least one circuit object relative to another circuit object of different object type, said predetermined layout strategy predefined and previously stored as one of a plurality of layout strategies representing a plurality of defining sets of expected circuit objects; and, a layout object management unit coupled to said layout object acquisition unit and said circuit editing tool, said layout object management unit being programmably configured to automatically: detect an editing operation imposed by said circuit editing tool on at least one circuit object within said layout object; and, adaptively adjust said layout object responsive to editing operation detected, in accordance with said layout strategy, wherein the electronic circuit design represents an electronic circuit to be produced.

7. The system as recited in claim 6 , wherein said placement scheme of said predetermined layout strategy includes relative margin and spacing attributes to be preserved between at least neighboring pairs of said circuit objects when schematically represented within said layout object.

8. The system as recited in claim 7 , wherein said interconnect routing scheme of said predetermined layout strategy defines at least one of: a bypass capacitor rail sub-circuit, a Thevenin termination sub-circuit; a pull-up voltage coupling sub-circuit; a pull-down voltage coupling sub-circuit; and, a filter sub-circuit.

9. The system as recited in claim 7 , wherein said layout object management unit executes at least one of the following adaptive actions within a schematic representation of the electronic circuit design: move said layout object; rotate said layout object; re-size said layout object; re-format the margin or spacing attributes of said layout object; re-arrange the circuit objects of said layout object; reconstitute the circuit objects of said layout object; and, re-connect the reconstituted circuit objects of said layout object.

10. The system as recited in claim 9 , wherein said layout object acquisition unit is selectively executable to merge a plurality of said layout objects within a schematic representation of the electronic circuit design.

11. The system as recited in claim 9 , wherein said layout object acquisition unit is executable to associate said layout object with a parent circuit object selected from the schematic representation of the electronic circuit design, and said layout object management unit conditionally maintains said layout object within the electronic circuit design based on said parent circuit object.

12. A method for automatically enforcing a schematic layout strategy applied to a group of schematically represented circuit objects of an electronic circuit design, comprising: executing a circuit editing tool to access a graphic database and electronically render schematic representations of the circuit objects responsive to user input; graphically displaying the schematic representations on one or more graphic pages within a graphic user interface on a display; executing a processor to selectively apply, responsive to user input, a predetermined layout strategy to at least one group of circuit objects selected from a pre-existing portion of a schematic representation of the electronic circuit design to reconfigure said group of circuit objects into a layout object corresponding to the predetermined layout strategy, said group of circuit objects including circuit objects of differing object types, said predetermined layout strategy including a defining set of expected circuit objects and a defining set of placement and interconnection routing schemes for the schematic representation of the grouped circuit objects, one relative to the other, said placement scheme placing at least one circuit object relative to another circuit object of different object type, said predetermined layout strategy predefined and previously stored as one of a plurality of layout strategies representing a plurality of defining sets of expected circuit objects; and, executing a processor to adaptively reconfigure said layout object in accordance with the layout strategy thereof automatically responsive to an editing operation being imposed on at least one circuit object within said layout object, wherein the electronic circuit design represents an electronic circuit to be produced.

13. The method as recited in claim 12 , wherein said placement scheme of said predetermined layout strategy includes relative margin and spacing attributes to be preserved between at least neighboring pairs of said circuit objects when schematically represented within said layout object.

14. The method as recited in claim 13 , wherein said interconnect routing scheme of said predetermined layout strategy defines at least one of: a bypass capacitor rail sub-circuit, a Thevenin termination sub-circuit; a pull-up voltage coupling sub-circuit; a pull-down voltage coupling sub-circuit; and, a filter sub-circuit.

15. The method as recited in claim 12 , further comprising: merging a plurality of said layout objects within a schematic representation of the electronic circuit design.

16. The method as recited in claim 12 , further comprising: associating said layout object with a parent circuit object selected from the schematic representation of the electronic circuit design; and, conditionally maintaining said layout object within the electronic circuit design based on said parent circuit object.

17. The method as recited in claim 12 , wherein said graphic database includes netlist data defining the structure and intercoupling of circuit objects in said layout object.