Expedited Servicing of Store Operations in a Data Processing System

1. A processing unit, comprising: a processor core including: an instruction sequencing unit that orders instructions for execution; and an execution unit that generates a store operation by executing a store instruction in an instruction sequence; a cache memory including a cache array and a store queue for buffering store operations to be serviced with respect to the cache array; and marking logic within at least one of set including the processor core and the cache memory, wherein the marking logic selectively marks the store operation as a high priority store operation, wherein the marking logic marks the store operation as a high priority store operation in response to detecting, in the instruction sequence, a barrier instruction that precedes the store instruction in program order and that includes a field set to indicate the store operation should be accorded high priority, and wherein the marking logic refrains from marking the store operation as a high priority store operation in response to not detecting, in the instruction sequence, a barrier instruction that precedes the store instruction in program order and that includes a field set to indicate the store operation should be accorded high priority; wherein the cache memory expedites handling of the store operation in the store queue in response to the store operation being marked as a high priority store operation and otherwise refrains from expediting handling of the store operation in the store queue.

2. The processing unit of claim 1 , wherein the marking logic includes core marking logic within the processor core.

3. The processing unit of claim 1 , wherein the marking logic includes marking logic within the cache memory.

4. The processing unit of claim 1 , and further comprising: store queue dispatch logic that records the store operation in an entry of the store queue; and wherein the store queue dispatch logic expedites handling of the store operation by reducing a duration of store gathering applied to the entry of the store queue in response to the store operation being marked as a high priority store operation.

5. The processing unit of claim 4 , wherein reducing the duration of the store gathering comprises terminating store gathering for the entry.

6. The processing unit of claim 1 , and further comprising: store queue dispatch logic that records the store operation in an entry of the store queue; and read-claim dispatch logic that expedites handling of the store operation by preferentially selecting the entry of the store queue for dispatch for servicing by reference to the cache array in response to the store operation being marked as a high priority store operation.

7. A data processing system, comprising: a plurality of processing units in accordance with claim 1 ; and an interconnect fabric coupling the plurality of processing units.

8. A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a processor core including: an instruction sequencing unit that orders instructions for execution; and an execution unit that generates a store operation by executing a store instruction in an instruction sequence; a cache memory including a cache array and a store queue for buffering store operations to be serviced with respect to the cache array; and marking logic within at least one of set including the processor core and the cache memory, wherein the marking logic selectively marks the store operation as a high priority store operation, wherein the marking logic marks the store operation as a high priority store operation in response to detecting, in the instruction sequence, a barrier instruction that precedes the store instruction in program order and that includes a field set to indicate the store operation should be accorded high priority, and wherein the marking logic refrains from marking the store operation as a high priority store operation in response to not detecting, in the instruction sequence, a barrier instruction that precedes the store instruction in program order and that includes a field set to indicate the store operation should be accorded high priority; wherein the cache memory expedites handling of the store operation in the store queue in response to the store operation being marked as a high priority store operation and otherwise refrains from expediting handling of the store operation in the store queue.

9. The design structure of claim 8 , wherein the marking logic includes core marking logic within the processor core.

10. The design structure of claim 8 , wherein the marking logic includes marking logic within the cache memory.

11. The design structure of claim 8 , and further comprising: store queue dispatch logic that records the store operation in an entry of the store queue; and wherein the store queue dispatch logic expedites handling of the store operation by reducing a duration of store gathering applied to the entry of the store queue in response to the store operation being marked as a high priority store operation.

12. The design structure of claim 11 , wherein reducing the duration of the store gathering comprises terminating store gathering for the entry.

13. The design structure of claim 8 , and further comprising: store queue dispatch logic that records the store operation in an entry of the store queue; and read-claim dispatch logic that expedites handling of the store operation by preferentially selecting the entry of the store queue for dispatch for servicing by reference to the cache array in response to the store operation being marked as a high priority store operation.