Devices and Operation Methods for Configuring Data Strobe Signal in Memory Device

1. A non-volatile memory device, comprising: a memory core to store data, the data being output from the memory core according to an external clock signal; an input buffer to receive the external clock signal and to provide an input clock signal; a synchronization circuit to receive the input clock signal and to provide an output clock signal, the synchronization circuit synchronizing the output clock signal to the external clock signal, the synchronization circuit including a delay circuit; a data strobe output buffer to receive the output clock signal and to provide a data strobe signal indicating the data output from the memory core is available for access, the data strobe signal having a signal delay configurable relative to the external clock signal; a clocked circuit element coupled to the memory core to receive the data output from the memory core and the output clock signal and to output the data in synchronism with the output clock signal; and a delay control circuit to provide a delay control signal to the delay circuit, the delay circuit being responsive to the delay control signal, to modify the signal delay of the data strobe signal.

2. The non-volatile memory device according to claim 1 , wherein the delay circuit includes a plurality of signal delay components; and a bypass circuit to bypass at least one of the plurality of signal delay components to modify the signal delay relative to the external clock signal, wherein the signal delay is determined by a number of the signal delay components bypassed, the number of bypassed signal delay components being determined by the delay control signal.

3. The non-volatile memory device according to claim 1 , wherein the delay circuit includes a plurality of signal delay components each adjusted according to the delay control signal to modify the signal delay.

4. The non-volatile memory device according to claim 1 , wherein the delay control circuit is configured to provide an output delay control signal, the non-volatile memory device further including an output delay circuit responsive to the output delay control signal to modify a signal delay of the data strobe signal relative to the data.

5. The non-volatile memory device according to claim 1 , wherein the delay control circuit includes a volatile memory for storing the delay control signal.

6. The non-volatile memory device according to claim 5 , wherein the memory core includes a memory array to store the delay control signal and; a logic control unit to control a loading, from the memory array, of the stored delay control signal into the volatile memory during a power-on or reset (POR) process.

7. The non-volatile memory device according to claim 5 , wherein the delay control circuit is coupled to a command interface to receive the delay control signal.

8. The non-volatile memory device according to claim 6 , wherein the delay control circuit is coupled to a command interface to receive the delay control signal and a memory write command to store the delay control signal.

9. The non-volatile memory device according to claim 1 , wherein the delay circuit is coupled to receive the output clock signal and to provide an output clock feedback signal; the synchronization circuit further including: a phase detector to receive the output clock feedback signal and the input clock signal, and to determine a phase difference between the output clock feedback signal and the input clock signal; and a shift register, controlled by the phase detector, to determine a delay length of a delay line, the delay line coupled to receive the input clock signal and to provide the output clock signal.

10. The non-volatile memory device according to claim 1 , wherein the delay circuit is coupled to receive the output clock signal and to provide an output clock feedback signal; the synchronization circuit further including: a phase detector to receive the output clock feedback signal and the input clock signal, and to determine a phase difference between the output clock feedback signal and the input clock signal; an oscillator, controlled by the phase detector, to provide the output clock signal; and a filter, coupled to the phase detector and the oscillator, to limit noise in the input clock signal.

11. The non-volatile memory device according to claim 1 , wherein the input buffer has a first delay length; and the delay circuit has a second delay length and a configurable delay length, the configurable delay length being modified according to the delay control signal; the synchronization circuit further including: a forward delay line having a third delay length; a backward delay line having a fourth delay length; a mirror control circuit to match the fourth delay length to the third delay length; and an internal buffer having a fifth delay length, wherein a sum of the first, second, third, fourth, and fifth delay lengths is an integer multiple of a duration of a full clock cycle of the external clock signal.

12. The non-volatile memory device according to claim 1 , wherein the delay circuit is coupled to receive the input clock signal provided by the input buffer.

13. The non-volatile memory device according to claim 1 , wherein the memory core is a flash memory.

14. A circuit to synchronize clock signals, comprising: a synchronization circuit to receive an input clock signal and to provide an output clock signal, the synchronization circuit synchronizing the output clock signal to an external clock signal, the synchronization circuit including a delay circuit; a strobe output buffer to receive the output clock signal and to provide a strobe signal, the strobe signal having a signal delay configurable relative to the external clock signal; and a delay control circuit to provide a delay control signal to the delay circuit, the delay circuit being responsive to the delay control signal, to modify the signal delay of the strobe signal.

15. The circuit according to claim 14 , wherein the synchronization circuit further includes a delay line to receive the input clock signal and to provide the output clock signal; a shift register, coupled to the delay line, to determine a delay length of the delay line; a phase detector to control the shift register; and a feedback loop including the delay circuit, the feedback loop coupled to the delay line and the phase detector.

16. The circuit according to claim 14 , wherein the delay circuit is coupled to receive the output clock signal and to provide an output clock feedback signal; the synchronization circuit further including: a phase detector to receive the output clock feedback signal and the input clock signal, and to determine a phase difference between the output clock feedback signal and the input clock signal; an oscillator, controlled by the phase detector, to provide the output clock signal; and a filter, coupled to the phase detector and the oscillator, to limit noise in the input clock signal.

17. A circuit to synchronize clock signals, comprising: an input buffer to receive an external clock signal and to provide an input clock signal, the input buffer having a first delay length; a synchronization circuit to receive the input clock signal and to provide an output clock signal, the synchronization circuit synchronizing the output clock signal to the external clock signal, the synchronization circuit including: a delay circuit having a second delay length and a configurable delay length, a forward delay line having a third delay length, a backward delay line having a fourth delay length, a mirror control circuit to match the fourth delay length to the third delay length, and an internal buffer having a fifth delay length, wherein a sum of the first, second, third, fourth, and fifth delay lengths is an integer multiple of a duration of a full clock cycle of the external clock signal; a strobe output buffer to receive the output clock signal and to provide a strobe signal, the strobe signal having a signal delay configurable relative to the external clock signal; and a delay control circuit to provide a delay control signal to the delay circuit of the synchronization circuit, the delay circuit being responsive to the delay control signal to adjust the configurable delay length of the delay circuit, to modify the signal delay of the strobe signal.

18. A method for configuring a signal delay in a non-volatile memory device, comprising: receiving an external clock signal; providing a data strobe signal indicating data stored in the non-volatile memory is available for access, the data strobe signal having a signal delay configurable relative to the external clock signal; and providing a memory operation command to the non-volatile memory device to modify the signal delay.

19. The method according to claim 18 , wherein providing the memory operation command includes: providing a memory write command; and providing a delay control signal to modify the signal delay of the data strobe signal.