Read Threshold Calibration for Ldpc

1. An apparatus, comprising: a controller coupled to a low-density-parity-check (LDPC) decoder, wherein the LDPC decoder is coupled to a memory, the controller configured to: select read threshold sets (RTSs); determine log-likelihood ratios (LLRs) based on a number of decisions that correspond to each of a number of bins associated with the selected RTSs; decode LDPC codewords based, at least in part, on the determined LLRs; and identify a plurality of initial read thresholds (IRTs) around a transition between voltage distributions corresponding to respective data states.

2. The apparatus of claim 1 , wherein the controller is configured to identify a RTS of the selected RTSs that yields a least number of failed codewords decoded using the determined LLRs.

3. The apparatus of claim 2 , wherein the controller is configured to identify a RTS of the selected RTSs that yields a least number of failed codewords decoded based, at least in part, on a determination of a good read threshold set (GRTS) for each page of a memory.

4. The apparatus of claim 1 , wherein the controller is configured to record a quantity of LDPC codewords cleared.

5. The apparatus of claim 1 , wherein the controller is configured to select RTSs as subsets from a plurality of initial read thresholds (IRTs) around a transition between voltage distributions corresponding to respective data states.

6. The apparatus of claim 5 , wherein the controller is configured to select RTSs as unique subsets from the plurality of IRTs by selecting as an RTS each unique group of N soft read thresholds from M IRTs, wherein N and M are numbers greater than zero.

7. The apparatus of claim 1 , wherein the controller is configured to identify a plurality of initial soft read thresholds around a transition between voltage distributions corresponding to two data states.

8. An apparatus, comprising: a controller configured to: record a quantity of low-density parity-check (LDPC) codewords that clear, the codewords associated with each of a plurality of sets of N soft read thresholds; identify at least one of the plurality of sets of N soft read thresholds that clears a largest quantity of codewords for each of a plurality of memory portions; and form a ranked list of sets of N soft read thresholds based on quantity of the plurality of memory portions for which sets of N soft read thresholds clears the largest quantity of codewords, wherein N is a number greater than zero.

9. The apparatus of claim 8 , wherein the controller is configured to determine a read threshold list (RTL), wherein a highest-ranked member of the RTL is a highest ranked set of N soft read thresholds from the ranked list.

10. The apparatus of claim 9 , wherein the controller is configured to determine a second highest-ranked member of the RTL is a highest ranked set of N soft read thresholds from the ranked list that clears a maximum quantity of codewords for one of the plurality of memory portions for which the first member of the RTL does not clear a maximum quantity of codewords.

11. The apparatus of claim 10 , wherein a member of the RTL is a highest ranked set of N soft read thresholds from the ranked list that clears a maximum quantity of codewords for at least one of the plurality of memory portions for which higher-ranked members of the RTL do not clear a maximum quantity of codewords.

12. The apparatus of claim 8 , wherein the controller is configured to decode LDPC codewords using at least member of the RTL.

13. The apparatus of claim 12 , wherein the controller is configured to decode an LDPC codeword using a highest-ranked member of the RTL.

14. The apparatus of claim 12 , wherein the controller is configured to decode LDPC codewords successively using members of the RTL in ranked order.

15. The apparatus of claim 8 , wherein the controller is configured to periodically re-determine a new RTL based on a quantity of codewords not cleared using any member of the RTL during decoding.

16. An apparatus, comprising: a memory; a low-density-parity-check (LDPC) encoder coupled to the memory; a LDPC decoder coupled to the memory; and a controller comprising control circuitry coupled to the LDPC encoder, the controller configured to: identify a plurality of initial read thresholds (IRTs) between data states; select subsets of the plurality of IRTs as read threshold sets (RTSs); determine log-likelihood-ratios (LLRs) based on a number of decisions that correspond to a number of bins associated with each RTS; and identify initial read thresholds (IRTs) around a transition between voltage distributions corresponding to respective data states.

17. The apparatus of claim 16 , wherein the LDPC encoder is configured to: receive unencoded data from a host coupled to the controller; and encode the received data to generate LDPC codewords.

18. The apparatus of claim 16 , wherein the LDPC decoder is configured to decode LDPC codewords based, at least in part, on the determined LLRs.

19. The apparatus of claim 16 , wherein at least one IRT is identified based on the at least one IRT yielding a lowest residual bit error rate.

20. The apparatus of claim 16 , wherein the controller is configured to: determine that a particular subset of the plurality of IRTs yields a least number of failed decoded codewords; and add the particular subset of the plurality of IRTs to a ranked list.