Energy-Focused Compiler-Assisted Branch Prediction

1. A memory device having instructions stored thereon that, in response to execution by a processor, cause the processor to perform operations to: access control information of an instruction sequence at runtime, the control information added in the instruction sequence prior to runtime to prevent coded information corresponding to a control-flow changing instruction from being decoded in a pipeline of the processor at runtime; and use the control information to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and to fetch an instruction corresponding to the path.

2. The memory device of claim 1 , wherein the control information comprises part of a payload of a coprocessor instruction.

3. The memory device of claim 1 , wherein the control information comprises code to select a dynamic branch prediction mechanism.

4. The memory device of claim 1 , wherein the control information is configured to stall fetching until a second control-flow changing instruction is executed that is not predictable statically or dynamically.

5. The memory device of claim 1 , wherein the control information comprises static information that suggests at least one of plural dynamic prediction mechanisms.

6. The memory device of claim 1 , wherein the control information specifies a condition under which a control-flow change at an end of the instruction sequence should occur.

7. The memory device of claim 1 , wherein the control information comprises part of an instruction configured to affect at least one of processor efficiency or processor energy consumption.

8. A system for use with a processor, the system comprising: microarchitecture capable of accessing control information of an instruction sequence at runtime, the control information added in the instruction sequence prior to runtime to prevent coded information corresponding to a control-flow changing instruction from being decoded in a pipeline of the processor at runtime; and the microarchitecture capable of using the control information to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and to fetch an instruction corresponding to the path.

9. The system of claim 8 , wherein the control information comprises part of a payload of a coprocessor instruction.

10. The system of claim 8 , wherein the control information comprises code to select a dynamic branch prediction mechanism.

11. The system of claim 8 , wherein the control information is configured to stall fetching until a second control-flow changing instruction is executed that is not predictable statically or dynamically.

12. The system of claim 8 , wherein the control information comprises static information that suggests at least one of plural dynamic prediction mechanisms.

13. The system of claim 8 , wherein the control information specifies a condition under which a control-flow change at an end of the instruction sequence is to occur.

14. The system of claim 8 , wherein the control information comprises part of an instruction configured to affect at least one of processor efficiency or processor energy consumption.

15. A method for use with a processor, the method comprising: with respect to an instruction sequence including a control-flow changing instruction to affect a control-flow of the instruction sequence to which control information has been added, removing the control-flow changing instruction from the instruction sequence; wherein the control information is to be utilized at runtime to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and to fetch an instruction corresponding to the path.

16. The method of claim 15 , wherein the control information comprises part of an instruction configured to affect at least one of processor efficiency or processor energy consumption.

17. The method of claim 15 , wherein the control information comprises part of a payload of a coprocessor instruction.

18. The method of claim 15 , wherein the control information includes static instructions, and wherein the processor is configured to remove the static instructions in a prefetch buffer at runtime to prevent the static instructions from entering a pipeline of the processor.

19. The method of claim 15 , wherein the control information comprises code to select a dynamic branch prediction mechanism at runtime.

20. The method of claim 15 , wherein the control information comprises static information that suggests at least one of plural dynamic prediction mechanisms.