Voltage Mode Drivers and Electronic Apparatus Having the Same

1. A voltage mode driver comprising: a voltage regulator; and a ripple compensation unit connected to an output terminal of the voltage regulator and configured to: compare a current data bit of a data pattern with a previous data bit of the data pattern in synchronization with a clock signal; generate a control signal when the current data bit is equal to the previous data bit; and apply a ground voltage to the output terminal in response to the control signal.

2. The voltage mode driver of claim 1 , further comprising: a first switch connected between a first node and a second node; a first resistor connected between the second node and a third node; a second switch connected between the first node and a fourth node; a second resistor connected between the fourth node and a fifth node; a third switch connected between a sixth node and a seventh node; a third resistor connected between the third node and the sixth node; a fourth switch connected between an eighth node and the seventh node; and a fourth resistor connected between the fifth node and the eighth node, wherein the output terminal of the voltage regulator is connected to the first node and a ground voltage is applied to the seventh node.

3. The voltage mode driver of claim 2 , further comprising a receiver connected to the voltage mode driver by a transmission line, wherein each of the first to fourth resistors has a resistance value for matching an impedance of the receiver.

4. The voltage mode driver of claim 1 , wherein the ripple compensation unit receives the data pattern and extracts the previous data bit and the current data bit from the data pattern.

5. The voltage mode driver of claim 4 , wherein the ripple compensation unit operates in synchronization with a rising edge and a falling edge of the clock signal and a period of the clock signal is a unit interval of the data pattern.

6. The voltage mode driver of claim 4 , wherein a width of the control signal corresponds to a data transmission rate of the data pattern.

7. The voltage mode driver of claim 4 , wherein the voltage mode driver transmits the data pattern to a receiver through a transmission line.

8. A voltage mode driver comprising: a voltage regulator; and a replica circuit connected to an output terminal of the voltage regulator and configured to: compare a current data bit of a data pattern with a previous data bit of the data pattern in synchronization with a clock signal; generate a first control signal and a second control signal when the current data bit is equal to the previous data bit; and apply a ground voltage to the output terminal in response to the first control signal or the second control signal.

9. The voltage mode driver of claim 8 , further comprising: a first switch connected between a first node and a second node; a first resistor connected between the second node and a third node; a second switch connected between the first node and a fourth node; a second resistor connected between the fourth node and a fifth node; a third switch connected between a sixth node and a seventh node; a third resistor connected between the third node and the sixth node; a fourth switch connected between an eighth node and the seventh node; and a fourth resistor connected between the fifth node and the eighth node, wherein the output terminal of the voltage regulator is connected to the first node and a ground voltage is applied to the seventh node.

10. The voltage mode driver of claim 9 , wherein the replica circuit comprises: a fifth switch connected between the first node and a ninth node; a fifth resistor connected between the ninth node and a tenth node; a sixth switch connected between the first node and an eleventh node; a sixth resistor connected between the eleventh node and a twelfth node; a seventh resistor connected between the tenth node and a thirteenth node; a seventh switch connected between the thirteenth node and a fourteenth node; an eighth resistor connected between the twelfth node and a fifteenth node; and an eighth switch connected between the fourteenth node and the fifteenth node, wherein the ground voltage is applied to the fourteenth node, wherein the fifth switch and the eighth switch are activated in response to the first control signal, and wherein the sixth switch and the seventh switch are activated in response to the second control signal.

11. The voltage mode driver of claim 10 , further comprising a receiver connected to the voltage mode driver by a transmission line, wherein each of the first to eighth resistors has a resistance value for matching an impedance of the receiver.

12. The voltage mode driver of claim 8 , wherein the replica circuit receives the data pattern and extracts the previous data bit and the current data bit from the data pattern.

13. The voltage mode driver of claim 12 , wherein the replica circuit operates in synchronization with a rising edge and a falling edge of the clock signal and a period of the clock signal is a unit interval of the data pattern.

14. The voltage mode driver of claim 12 , wherein a width of the first control signal or the second control signal corresponds to a data transmission rate of the data pattern.

15. The voltage mode driver of claim 8 , wherein each of the first control signal and the second control signal have an inverse phase to each other.

16. A voltage mode driver comprising: a voltage regulator; a switching circuit connected to an output terminal of the voltage regulator, connected to an output terminal of the voltage mode driver, and configured to output a data pattern, wherein the switching circuit comprises a plurality of resistors which generate a first electrical load; and a data-dependent ripple generation circuit connected to the output terminal of the voltage regulator and configured to generate uniform ripple in the output of the voltage mode driver.

17. The voltage mode driver of claim 16 , wherein the data-dependent ripple generation circuit is configured to generate uniform ripple in the output of the voltage mode driver by connecting a second electrical load to the output terminal of the voltage mode driver in response to a comparison of a current data bit of the data pattern with a previous data bit of the data pattern in synchronization with a clock signal.

18. The voltage mode driver of claim 17 , wherein the first electrical load and the second electrical load are substantially the same.

19. The voltage mode driver of claim 17 , wherein the data-dependent ripple generation circuit comprises: a load resistor connected between the output terminal of the voltage mode driver and a first node; a first switch connected between the first node and a second node, wherein the first switch is controlled by a control signal; and a data pattern analysis unit configured to: compare the current data bit of the data pattern with the previous data bit of the data pattern in synchronization with the clock signal; and generate the control signal when the current data bit is equal to the previous data bit.

20. The voltage mode driver of claim 17 , wherein the switching circuit comprises: a first switch connected between a first node and a second node; a first resistor connected between the second node and a third node; a second switch connected between the first node and a fourth node; a second resistor connected between the fourth node and a fifth node; a third switch connected between a sixth node and a seventh node; a third resistor connected between the third node and the sixth node: a fourth switch connected between an eighth node and the seventh node; and a fourth resistor connected between the fifth node and the eighth node, wherein the output terminal of the voltage regulator is connected to the first node, and wherein the ripple compensation circuit comprises: a data pattern analysis unit configured to: compare the current data bit of the data pattern with the previous data bit of data pattern in synchronization with the clock signal; and generate a first control signal and a second control signal in synchronization with the clock signal when the current data bit is equal to the previous data bit; a fifth switch connected between the first node and a ninth node; a fifth resistor connected between the ninth node and a tenth node; a sixth switch connected between the first node and an eleventh node; a sixth resistor connected between the eleventh node and a twelfth node; a seventh resistor connected between the tenth node and a thirteenth node; a seventh switch connected between the thirteenth node and a fourteenth node; an eighth resistor connected between the twelfth node and a fifteenth node; an eighth switch connected between the fourteenth node and the fifteenth node; a first capacitor between, the tenth node and a sixteenth node; and a second capacitor between the twelfth node and a seventeenth node, wherein the fifth switch and the eighth switch are activated in response to the first control signal, and wherein the sixth switch and the seventh switch are activated in response to the second control signal, and wherein the voltage mode driver further comprises: a third capacitor between the third node and an eighteenth node; and a fourth capacitor between the fifth node and a nineteenth node.